Input/output subsystem having an integrated advanced programmable interrupt controller for use in a personal computer

A computer system comprising:

• a host processor containing a local advanced programmable interrupt controller (APIC);
• a host chipset connected to the host processor by a host bus;
• an input/output (I/O) subsystem connected to the host chipset by a primary PCI bus and connected to the local APIC of the host processor by an APIC bus;
• an I/O processor provided within the I/O subsystem, for receiving APIC interrupt signals from I/O devices, emulating APIC functionality, and communicating with the local APIC of the host processor over the APIC bus;
• an interrupt controller provided within the I/O subsystem, for receiving at its input non-PCI interrupt signals and PCI interrupt signals and providing to said I/O processor for processing said non-PCI interrupt signals and PCI interrupt signals;
• and
• a set of multiplexers receiving at its input non-PCI interrupt signals and PCI interrupt signals and selectively directing said non-PCI interrupt signals and PCI interrupt signals to one of said interrupt controller and said primary PCI bus according to a selection signal from said I/O processor.

A computer system comprising:

• a host platform;
• a PCI expansion box having a plurality of expansion slots for I/O devices;
• a PCI bus interconnecting the host platform and the PCI expansion box;
• an I/O processor running an emulation program, within the PCI expansion box, for receiving non-PCI interrupt signals from the I/O devices of the expansion slots, for encoding the non-PCI interrupts as PCI data signals, and for forwarding the encoded non-PCI interrupts to the host platform over the PCI bus;
• an interrupt controller provided within the PCI expansion box, for receiving at its input non-PCI interrupt signals and providing to said I/O processor for processing said non-PCI interrupt signals;
• a set of multiplexers receiving at its input non-PCI interrupt signals and PCI interrupt signals and selectively directing said non-PCI interrupt signals and PCI interrupt signals to one of said interrupt controller and said primary PCI bus according to a selection signal from said I/O processor;
• and
• a host processor within the host platform, for receiving and decoding the encoded non-PCI interrupt data signals and for converting those signals to advanced programmable interrupt controller (APIC) interrupt signals.

A computer system comprising:

• a host platform;
• a PCI expansion box having a plurality of expansion slots for I/O devices;
• a PCI bus interconnecting the host platform and the PCI expansion box;
• an advanced programmable interrupt controller (APIC) bus interconnecting the host platform and the PCI expansion box;
• an I/O Processor running an APIC emulation program within the PCI expansion box, for receiving non-PCI interrupts from the I/O devices, for converting the interrupts to APIC interrupts, and for forwarding the APIC interrupts over the APIC bus;
• an interrupt controller provided within the PCI expansion box, for receiving at its input non-PCI interrupt signals and providing to said I/O processor for processing said non-PCI interrupt signals;
• a set of multiplexers receiving at its input non-PCI interrupt signals and PCI interrupt signals and selectively directing said non-PCI interrupt signals and PCI interrupt signals to one of said interrupt controller and said primary PCI bus according to a selection signal from said I/O processor;
• and
• an host processor having a local APIC within the host platform, for receiving and processing the APIC interrupts forwarded over the APIC bus.