Apparatus method and system for peripheral component interconnect bus using accelerated graphics port logic circuits

A method, in a computer system, of configuring a core logic chip set for either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus, said method comprising the steps of:

• providing a central processing unit connected to a host bus;
• providing a random access memory connected to a random access memory bus;
• providing a core logic chip set connected to the host bus and the random access memory bus;
• configuring said core logic chip set as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus;
• and
• configuring said core logic chip set as a fourth interface bridge between the host bus and a second 32 bit peripheral component interconnect bus and a fifth interface bridge between the random access memory bus and the second 32 bit peripheral component interconnect bus when a configuration signal is applied to said core logic chip set.

A core logic chip set configurable for either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus, comprising:

• a core logic chip set adapted for connection to a central processing unit host' bus, random access memory bus, a first peripheral component interconnect bus, and an accelerated graphics port bus or a second peripheral 32 bit component interconnect bus;
• said core logic chip set configured as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and the first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus;
• said core logic chip set configured as a fourth interface bridge between the host bus and the second 32 bit peripheral component interconnect bus;
• and
• said core logic chip set configured as a fifth interface bridge between the random access memory bus and the second 32 bit peripheral component interconnect bus.