Interface device for XT/AT system devices on high speed local bus

A host bus interface device for interfacing a processor coupled to a host bus to at least one I/O device and a high speed bus, comprising:

• a host controller coupled between the host bus and the high speed bus;
• at least one I/O device coupled to the host controller;
• the host controller configured to provide an interface between the processor and the at least one I/O device and between the processor and the high speed bus;
• and
• a buffer device coupled between the host controller and the at least one I/O device;
• the host controller including a decoder coupled to the buffer device and configured to decode I/O transactions from the processor to the at least one I/O device.

A computer system comprising:

• a host bus;
• a high speed bus;
• a low speed bus;
• a processor coupled to the host bus;
• a host bus bridge coupled between the host bus and the high speed bus;
• and
• a low speed bus bridge coupled between the high speed bus and the low speed bus;
• the host bus bridge comprising,
• a host controller coupled between the host bus and the high speed bus,
• I/O devices coupled to the host controller, the I/O devices including an interrupt controller, a timer device, and a clock device,
• the host controller configured to provide an interface between the processor and the I/O devices and between the processor and the high speed bus, and
• a buffer device coupled between the host controller and the I/O devices,
• the host controller including a decoder coupled to the buffer device and configured to decode I/O transactions from the processor to at least one of the I/O devices.

A computer system comprising:

• a host bus;
• a high speed bus;
• a low speed bus;
• a processor coupled to the host bus;
• a host bus bridge coupled between the host bus and the high speed bus;
• and
• a low speed bus bridge coupled between the high speed bus and the low speed bus;
• the host bus bridge including,
• a host bus and the high speed bus,
• at least one I/O device coupled to the host controller,
• the host configured to provide an interface between the processor and the at least one I/O device and between the processor and the high speed bus, and
• a buffer device coupled between the host controller and the at least one I/O device,
• the host controller including a decoder coupled to the buffer device and configured to decode I/O transactions from the processor to the at least one I/O device.