Network for transferring consecutive packets between processor and memory with a reduced blocking time

An interconnection network for use between a processor unit and a memory unit of a parallel computer system in transferring data sequences from a first plurality of input ports to a second plurality of output ports with each data sequence of said data sequences composed of consecutive packets and routed to one of said input ports that is specified by a leading packet of said consecutive packets, said interconnection network comprising:

• input buffer means, wide enough to accommodate two data packets simultaneously, connected to said input ports for storing at least a leading portion of said data sequence with the consecutive packets of said leading portion stored as primary stored packets and for simultaneously producing said primary stored packets in one machine cycle in a packet-parallel fashion as supply packets;
• input selector means connected to said input buffer means for selecting primary selected packets from said supply packets to produce said primary selected packets and for selecting, as soon as a remaining portion of said data sequence reaches said input buffer means, secondary selected packets from the consecutive packets of said remaining portion to produce said secondary selected packets;
• and
• output buffer means connected to said input selector means and to said output ports for storing said primary and said secondary selected packets collectively as secondary stored packets to produce said secondary stored packets as output packets for delivery to one of said output ports.