US 5,857,069 A · Technique for recovering defective memory

Abstract

A technique for improving the manufacturing yield of data processing memory. A memory array contains a known pattern of single-bit defects. Specifically, a first group of the memory cells contain flawless storage devices which are capable of being set to either of two possible stable states, i.e., a binary "1" or a binary "0." A second group of the memory cells contain the single-bit defects. These storage devices of the second group are capable of being set to only one of the two possible stable states. Before data is loaded into the memory, a coder codes the data such that bits to be loaded into the memory cells with bit defects match the state of the bit defect. The coder also generates code bits capable of decoding the coded data. A memory input-output circuit loads the code bits and the coded data blocks into the memory cells. When the memory input-output circuit accesses the memory, it passes the coded data blocks and the code bits to a decoder which uses the code bits to decode the data blocks.

Claims19

Dependent claims

A data processing apparatus comprising:

a memory having a plurality of memory cells each having storage circuitry for storing a bit therein, said storage circuitry of a first group of said memory cells capable of being set to two stable states, and said storage circuitry of a second group of said memory cells capable of being set to only one of either of said two stable states;
coding circuitry for coding data such that each said bit to be stored in said second group matches the stable state of said memory cell into which each said bit is to be stored, and for generating code bits capable of decoding said data;
and
decode circuitry connected to said memory for reading data from said memory and decoding said data in response to said code bits.

1 more element

An integrated circuit comprising:

a processor input-output circuit having terminal means for outputting data from said integrated circuit and for receiving data inputted to said integrated circuit;
a memory having a plurality of memory cells each having storage circuitry for storing a binary bit therein, said storage circuitry of a first group of said memory cells capable of being set into two stable states, and said storage circuitry of a second group of said memory cells having at least one bit defect such that each said memory cell of said second group is capable of being set into only one of either of said two stable states;
a control circuit connected to said memory for accessing selected segments of said memory, each segment having a plurality of said memory cells, said control circuit having write means for loading data blocks into each said segment and read means for reading data blocks stored in each said segment;
a data processor connected to said processor input-output circuit and said control circuit, said data processor having code circuitry for coding said data blocks such that said bits to be stored in said second group of said memory cells match the state of said memory cell into which each said bit is stored and for generating code bits capable of decoding said data blocks;
and
decode circuitry connected to said read means and responsive to said code bits for decoding said data blocks being read from said memory.

3 more elements

Dependencies are inferred from the claim text.

Technique for recovering defective memory

Life of this patent

Technique for recovering defective memory

Life of this patent

Abstract

Claims19