US 5,856,975 A · High speed single chip digital video network apparatus

Abstract

A high speed digital video network apparatus is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits. The interconnection includes a packet conversion logic which converts between a network protocol, such as Asynchronous Transfer Mode (ATM) packets, and the data protocol used to handle large data streams, such as Motion Picture Experts Group (MPEG) packets. The interconnection further includes a Virtual Channel Memory (VCM) for storing ATM cells for segmentation and reassembly, a Direct Memory Access (DMA) controller for connecting the VCR to the compression/decompression circuits, a Parallel Cell Interface (PCI) for connecting the VCM to an ATM network, a Pacing Rate Unit (PCU) for automatically reducing the maximum transmission rate in response to a sensed congestion condition in the network, and a Reduced Instruction Set Computer (RISC) microprocessor for controlling the DMA controller and transfers between the memory, a host and the ATM network, for performing segmentation and reassembly of Conversion Sublayer Payload Data Units (CD-PDUs), and for performing conversion between the ATM Protocol and the MPEG protocol. The compression/decompression and decoder/encoder circuits may utilize MPEG to compress digitized images and motion video into compact data streams that can be moved across networks with bandwidths too narrow to accommodate the uncompressed data. The operating program for the RISC microprocessor is stored in a volatile Instruction Random Access Memory (IRAM) in the form of firmware which can be downloaded at initialization.

Claims6

Dependent claims

A single chip digital video network apparatus, comprising on a single semiconductor substrate:

a physical layer circuit for interfacing to an asynchronous transfer mode (ATM) network;
an ATM cell interface circuit coupled to the physical layer circuit for receiving packets of data in an ATM network protocol format from the physical layer circuit;
a virtual channel RAM (VCR) coupled to the ATM cell interface circuit for storing packets of data;
a direct memory access-VCR (DMA-VCR) bus coupled to the VCR for transferring packets of data from the VCR;
a direct memory access (DMA) controller coupled to the DMA-VCR bus for controlling a transfer of packets of data from the VCR;
a random access memory for storing packets of data in an ATM network protocol format, the random access memory being coupled to the DMA controller;
an internal data bus coupled to the DMA controller for transferring packets of data from the DMA controller;
an ATM processing unit (APU) for converting data in the ATM network protocol format to an internal data format, said APU being coupled to the internal data bus;
a host data bus coupled to the DMA controller for transferring packets of data from the DMA controller;
a Motion Picture Experts Group (MPEG) data bus for transferring packets of data in an MPEG format;
a shared host RAM coupled to the host data bus and coupled to the MPEG data bus for storing data in the internal data format;
a video decoder coupled to the MPEG data bus for decoding MPEG full motion video data into a digital representation of a video signal;
and
an audio decoder coupled to the MPEG data bus for decoding MPEG audio data into a digital representation of an audio signal.

11 more elements

Dependencies are inferred from the claim text.

High speed single chip digital video network apparatus

Life of this patent

High speed single chip digital video network apparatus

Life of this patent

Abstract

Claims6