Semiconductor memory device with an improved hierarchical power supply line configuration

A semiconductor integrated circuit device comprising:

• a main power source line for transmitting a first power source voltage;
• a sub power source line;
• a switching transistor for electrically connecting said main power source line and said sub power source line in response to an operation cycle defining signal;
• an insulated gate type field effect transistor having a back gate, one conduction node connected to said main power source line, other conduction node connected to said sub power source line and a control electrode node connected to either said main power source line or said sub power source line so as to form a diode from a high potential side to a low potential side;
• a reference voltage generating circuit for applying a first reference voltage to said back gate of said insulated gate type field effect transistor, said first reference voltage being different in voltage level from the first power source voltage;
• and
• a logic gate operating using the voltage on said sub power source line as one operation power source voltage for performing a prescribed logic processing on an applied input signal for outputting.