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US 5,856,946 AGranted
Memory cell programming with controlled current injection
AssigneeAdvanced Micro Devices, Inc.
InventorsVei-Han Chan, Sameer Haddad, Chi Chang
Life of this patent
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Abstract
A memory with controlled gate current injection during memory cell programming wherein programming circuitry applies a time-varying voltage to a control gate of the memory cell during a programming cycle. The time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate during the programming cycle.
Claims16
A memory device, comprising:
- a memory cell having a control gate having a corresponding voltage V.sub.g,
- a floating gate formed over a substrate having a corresponding voltage V.sub.fg, and
- a first region and a second region formed in the substrate with a channel region therebetween;
- and
- circuitry that applies a time-varying voltage V.sub.g (t) to the control gate during a programming cycle on the memory cell such that the time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate, the time-varying voltage varying throughout the programming cycle on the memory cell;
- wherein said time-varying voltage V.sub.g (t) is applied such that said floating gate voltage V.sub.fg is represented by .alpha..sub.d *V.sub.d +.alpha..sub.g *(V.sub.g -.DELTA.V.sub.t), where .alpha..sub.d is a coupling coefficient from a drain region of one of said first and second regions to said floating gate, and .alpha..sub.g is a coupling coefficient from said control gate to said floating gate.
3 more elements
A memory device, comprising:
- a flash memory cell having,
- a control gate,
- a floating gate having a corresponding voltage V.sub.fg ;
- a channel region;
- and
- a ramp voltage generator in communication with the control gate, the ramp voltage generator applies an increasing time-varying voltage V.sub.g (t) to the control gate throughout a programming cycle on the memory cell such that the time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate, the time-varying voltage varying throughout the programming cycle on the memory wherein said time-varying voltage V.sub.g (t) is applied such that said floating gate voltage V.sub.fg is represented by .alpha..sub.d *V.sub.d +.alpha..sub.g *(V.sub.g -.DELTA.V.sub.t), where .alpha..sub.d is a coupling coefficient from a drain region to said floating gate, and .alpha..sub.g is a coupling coefficient from said control gate to said floating gate.
3 more elements
A method for programming a flash memory cell, the flash memory cell including a source, a drain, a control gate, a floating gate having a corresponding voltage V.sub.fg ;
- and a channel region, the method comprising the steps of:
- applying a first voltage to said drain;
- and
- applying an increasing time-varying second voltage V.sub.g (t) to the control gate during a programming cycle on the flash memory cell such that the time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate, the second voltage varying throughout the programming cycle on the flash memory cell wherein said V.sub.g (t) is applied such that said floating gate voltage V.sub.fg is represented by .alpha..sub.d *V.sub.d +.alpha..sub.g *(V.sub.g -.DELTA.V.sub.t), where .alpha..sub.d is a coupling coefficient from said drain to said floating gate, and .alpha..sub.g is a coupling coefficient from said control gate to said floating gate.
1 more element
Dependencies are inferred from the claim text.