Method for preventing sub-threshold leakage in flash memory cells to achieve accurate reading, verifying, and fast over-erased Vt correction

A method for repairing threshold voltages of a plurality of overerased cells in a plurality of bitlines in a flash memory, the method comprising:

• determining whether each bitline is an erased bitline, which contains cells having negative threshold voltages, or an unerased bitline, which does not contain cells having negative threshold voltages;
• selecting erased bitlines for controlling the threshold voltage distribution of the plurality of cells in the selected erased bitlines during an overerase repair operation;
• categorizing each of said plurality of cells in each selected erased bitline into first, second, and third regions based on a threshold voltage of each cell, wherein first region cells have a positive threshold voltage and were erased in the selected erased bitline, a second region cell has a negative threshold voltage, and third region cells have a positive threshold voltage higher than that of the first region cells and which were not selected for erasure in the selected erased bitline;
• applying a first wordline voltage and a first source voltage to the first region cells to maintain the positive threshold voltages of the first region cells as the second region cell is being repaired, wherein the first source voltage and the first wordline voltage bias a first floating gate voltage to be less than the first source voltage to prevent the first region cells from conducting current as the second region cell is being repaired;
• applying a second wordline voltage and a second source voltage to the second region cell, the second wordline voltage being a positive voltage to repair the second region cell by raising the threshold voltage of the second region cell to a positive value;
• applying a third wordline voltage and a third source voltage to each of the third region cells to maintain the positive threshold voltages of the third region cells as the second region cell is being repaired, wherein the third source voltage and the third wordline voltage bias a third floating gate voltage to be less than the third source voltage to prevent the third region cells from conducting current as the second region cell is being repaired;
• and
• repeating the categorizing and applying steps on the same cells in each selected bitline until all of the cells selected to be repaired become first region cells.

A method of eliminating sub-threshold leakage in cells of a flash memory device during one of a read operation and a verify operation comprising the steps of:

• selecting a bitline containing a plurality of cells, the plurality of cells including one selected cell and a plurality of non-selected cells;
• selecting a wordline corresponding to the selected cell;
• applying a wordline voltage to gates of each of the plurality of non-selected cells;
• applying a sourceline voltage to each sources of the plurality of non-selected cells so that the wordline voltage and the sourceline voltage bias a floating gate voltage within each of the non-selected cells to be less than the sourceline voltage to prevent the non-selected cells from conducting current as the selected cell is being operated upon;
• and
• performing said one operation on said selected cell while said ground wordline voltage and said positive sourceline voltage is being applied to each of said plurality of non-selected cells.