Self-converging over-erase repair method for flash EPROM
AssigneeAlliance Semiconductor Corporation
InventorsBruce L. Prickett, Jr., Ritu Shrivastava
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Abstract
A method of repairing over-erased flash EPROM cells (10) includes erasing the cells (12) and repairing the cells by a self-converging repair with a control gate bias (14), on a column by column basis. The self-converging repair includes grounding the sources (104) of the cells in a column, applying a pulsed bias voltage to the control gates of the cells (110), and a pulsed positive voltage to the drains of the cells (106). By varying the bias voltage at the control gate, the resulting threshold voltage of the cells after repair can be modulated to be greater than or less than an inherent steady state convergence value. Once one column of cells is repaired, the process is repeated on a subsequent column.
Claims24
In a flash electrically programmable read only memory (EPROM) device having a plurality of memory cells arranged in rows and columns, each memory cell having a first diffusion region, a second diffusion region, and a control gate, a method of repairing over-erased cells, comprising the steps of:
- (a) flash erasing at least a column of cells;
- (b) verifying the operation of the cells in the column;
- (c) in the event at least one cell in the column is over-erased, repairing the cells by grounding the first diffusion regions of the cells in the column, applying a positive bias voltage to the second diffusion regions of the cells in the column, and applying a non-zero, offset bias voltage to the control gates of the cells in the column.
In a flash electrically programmable read only memory (EPROMs) having a plurality of one transistor flash memory cells, each cell being coupled to a bit line by its drain and to a wordline by its control gate, a self-converging over-erase repair method, comprising the steps of:
- testing at least one bit line for over-erased cells;
- if an over-erased cell is detected in the one bit line, repairing the memory cells coupled to the bit line by coupling the sources of the memory cells coupled to the bit lines to ground, applying a bias voltage to the control gates of the memory cells, and applying a positive voltage to the bit line, and
- if no over-erased cells are detected in the one bit line, testing subsequent bit lines in the memory for over-erased cells, and repairing those bit lines having over-erased cells according to the above repair step.
In a flash electrically programmable read only memory (EPROMs) having a plurality of memory cells arranged in an array of rows and columns, each cell having a source, a drain, and a control gate, wherein the sources of the cells in the array are commonly coupled to a source node, the drains of the cells in a column are commonly coupled to a bit line, and the control gates of the cells in a row are commonly coupled to a word line, a method of flash erasing, comprising the steps of:
- (a) erasing the cells in the array;
- (b) selecting a column of cells by coupling the bit line of the column to a current sensing circuit, applying a deselect voltage to the control gate of each cell in the selected column, and coupling the source node to a common first source voltage;
- (c) comparing the current in the bit line to a maximum leakage current;
- (d) if the current in the bit line is greater than the maximum leakage current, repairing the cells in the column by coupling the bit line to a first drain bias voltage and the control gates of the cells in the column to a converge repair voltage, and then repeating step (c);
- and
- (e) if the current in the bit line is less than the maximum leakage current, repeating the above method beginning with step (b) on the remainder of the columns until all the cells in the entire array are repaired.
Dependencies are inferred from the claim text.