Scalable flash EEPROM memory cell and array
AssigneeIntegrated Memory Technologies, Inc.
InventorChing-Shi Jeng
Life of this patent
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Abstract
A scalable flash EEPROM cell has a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate has a first portion over the select gate and insulated therefrom, and a second portion over a second portion of the channel and over the source, and is between the select gate and the source. A control gate is over the floating gate and is insulated therefrom. A memory array using this memory cell is also disclosed.
Claims12
A method of programming a floating gate memory transistor having a drain and a source with a channel therebetween, a select gate extending over a first portion of said channel, and capacitively coupled thereto;
- a floating gate capacitively coupled to said select gate and to a second portion of said channel, between said select gate and said source;
- and a control gate capacitively coupled to said floating gate, said method comprising:
- applying a first positive voltage to said source;
- applying a second positive voltage to said select gate causing electrons to flow in said channel between said drain and source;
- and
- applying a third positive voltage to said control gate of sufficient magnitude to cause a voltage on said floating gate causing hot electron injection of said electrons flowing in said channel to be injected onto said floating gate.
A method of erasing a floating gate memory transistor having a drain and a source with a channel therebetween, a select gate extending over a first portion of said channel, and capacitively coupled thereto;
- a floating gate capacitively coupled to said select gate and to a second portion of said channel, between said select gate and said source;
- and a control gate capacitively coupled to said floating gate, said method comprising:
- applying a first positive voltage to said source;
- applying a ground voltage to said select gate;
- and
- applying a ground voltage to said control gate to cause electrons on said floating gate to Fowler-Nordheim tunnel to said source.
A method of erasing a floating gate memory transistor having a drain and a source with a channel therebetween, a select gate extending over a first portion of said channel, and capacitively coupled thereto;
- a floating gate capacitively coupled to said select gate and to a second portion of said channel, between said select gate and said source;
- and a control gate capacitively coupled to said floating gate, said method comprising:
- applying a first positive voltage to said source;
- applying a second voltage, to said select gate, wherein said second voltage is no more than ground voltage;
- and
- applying a negative voltage to said control gate to cause electrons on said floating gate to Fowler-Nordheim tunnel to said source.
A method of programming a floating gate memory transistor to one of a plurality of different bit levels, said transistor having a drain and a source with a channel therebetween, a select gate extending over a first portion of said channel, and capacitively coupled thereto;
- a floating gate capacitively coupled to said select gate and to a second portion of said channel, between said select gate and said source;
- and a control gate capacitively coupled to said floating gate, said method comprising:
- erasing said floating gate memory transistor to an erased state;
- applying a first positive voltage to said source;
- applying a second positive voltage to said select gate causing electrons to flow in said channel between said drain and source;
- and
- applying a third positive voltage to said control gate, said third positive voltage being one of a plurality of possible voltages that can be applied to said control gate, to cause one of a plurality of possible voltages on said floating gate causing one of a plurality of different amounts of hot electrons flowing in said channel to be injected onto said floating gate, thereby programming said floating gate to one of a plurality of different bit levels.
Dependencies are inferred from the claim text.