US 5,856,942 AGranted

Flash memory array and decoding architecture

AssigneeAplus Integrated Circuits, Inc.

InventorsPeter Wung Lee, Fu-Chang Hsu, Hsing-Ya Tsao

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Abstract

A flash memory circuit having a word line decoder with even and odd word line latches and a source line decoder with a source line latch is disclosed. The word line decoders and source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.

Claims7

Dependent claims

A method of memory operation for erasing and verifying the memory cells of one or more word lines in a flash memory circuit, comprising the steps of

A. selecting the word lines that are to be erased;
B. identifying memory cells that will be disturbed if the word lines selected in step
a. are applied an appropriate erase bias condition;
C. reading the data of the memory cells identified in step B. and storing the data in a temporary storage device;
D. setting up said appropriate erase bias condition for the memory cells of the word lines selected for erasing and non-erase bias conditions for the memory cells of other non-selected word lines;
E. applying an erase pulse to the word lines selected for erasing;
F. performing data verification for the memory cells of the word lines selected for erasing;
G. going to step I. if the memory cells of all the word lines selected for erasing have passed the data verification of step F.;
H. updating the selection of the word lines for erasing by excluding the word lines in which all memory cells have passed the data verification of step F. and returning to step D. if a pre-determined time limit is not exceeded, otherwise going to step P.;
I. reading new data of a first group of memory cells identified in step B. and executing data "1" verification for said first group of memory cells, said first group of memory cells having data value "1" stored in said temporary storage device;
J. continuing step L. if said data "1" verification of step I. succeeds, otherwise executing step K.;
K. post-programming data "1" to the memory cells of said first group and returning to step I. if said data "1" verification of step I. fails and a predetermined time limit is not exceeded, otherwise going to step P.;
L. reading new data of a second group of memory cells identified in step B. and executing data "0" verification for said second group of memory cells, said second group of memory cells having data value "0" stored in said temporary storage device;
M. going to step O. if said data "0" verification of step L. succeeds, otherwise executing step N.;
N. post-programming data "0" to the memory cells of said first group and returning to step L. if said data "0" verification of step L. fails and a predetermined time limit is not exceeded, otherwise going to step P.;
O. exiting said memory operation successfully;
P. exiting said memory operation and declaring said flash memory circuit defective.

14 more elements

A method of memory operation for erasing and verifying the memory cells of a plurality of segments of a word line in a flash memory circuit, comprising the steps of:

a. selecting the segments that are to be erased;
b. identifying the memory cells that will be disturbed if the segments selected in step a. are applied an appropriate erase bias condition;
c. reading the data of the memory cells identified in step b. and storing the data in a temporary storage device;
d. setting up said appropriate erase bias condition for the memory cells of the segments selected for erasing and non-erase bias conditions for the memory cells of other non-selected segments and non-selected word lines;
e. applying an erase pulse to the segments selected for erasing;
f. performing data verification for the memory cells of the segments selected for erasing;
g. going to step i. if the memory cells of all the segments selected for erasing have passed verification;
h. updating the selection of the segments for erasing by excluding the segments in which all memory cells have passed verification and returning to step d. if a pre-determined time limit is not exceeded, otherwise going to step p;
i. reading new data of a first group of memory cells identified in step b. and executing data "1" verification for said first group of memory cells, said first group of memory cells having data value "1" stored in said temporary storage device;
j. continuing step l. if said data "1" verification of step i. succeeds, otherwise executing step k.;
k. post-programming data "1" to the memory cells of said first group and returning to step i. if said data "1" verification of step i. fails and a predetermined time limit is not exceeded, otherwise going to step p.;
l. reading new data of a second group of memory cells identified in step b. and executing data "0" verification for said second group of memory cells, said second group of memory cells having data value "0" stored in said temporary storage device;
m. going to step o. if said data "0" verification of step l. succeeds, otherwise executing step n.;
n. post-programming data "0" to the memory cells of said first group and returning to step l. if said data "0" verification of step l. fails and a predetermined time limit is not exceeded, otherwise going to step p.;
o. exiting said memory operation successfully;
p. exiting said memory operation and declaring said flash memory circuit defective.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/884,926Filed 30 Jun 1997 · continuation in part
Priority: 5 Jun 1997
Granted: 5 Jan 1999
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

G11C 16/3427
Disturbance prevention or evaluation; Refreshing of disturbed memory data: circuits or methods to prevent or reduce disturbance of the state of a…
G11C 11/5621
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using charge storage in…
G11C 11/5628
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
G11C 11/5635
Programming or writing circuits; Data input circuits: erasing circuits