One-time programmable latch which allows volatile writes prior to permanent programming

A programmable latch circuit for storing a value, said circuit comprising:

• a first programmable device (28), said first programmable device being a field effect transistor (FET) device including a source terminal, a drain terminal and a gate terminal, said first programmable device further including a first capacitor in series with the gate terminal, one of either the source or drain terminal of the first programmable device being connected to a reference potential;
• a second programmable device (30), said second programmable device being an FET device including a source terminal, a drain terminal and a gate terminal, said second programmable device further including a second capacitor in series with the gate terminal, one of either the source or drain terminal of the second programmable device being connected to the reference potential;
• a first latch device (32), said first latch device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the first latch device being connected to the source or drain terminal of the first programmable device that is not connected to the reference potential and the other of the source or drain terminal of the first latch device being connected to a voltage source;
• a second latch device (34), said second latch device being an FET device including a source terminal, a drain terminal, and a gate terminal, one of either the source terminal or the drain terminal of the second latch device being connected to the source or drain terminal of the second programmable device that is not connected to the reference potential and the other of the source or drain terminal of the second latch device being connected to the voltage source;
• a third latch device (56), said third latch device being an FET device including a source terminal, a drain terminal, and a gate terminal, one of either the source or drain terminal of the third latch device being connected to the gate terminals of the first programmable device and the first latch device;
• a fourth latch device (64), said fourth latch device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the fourth latch device being connected to the gate terminals of the second programmable device and the second latch device;
• a fifth latch device (62), said fifth latch device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the fifth latch device being connected to the gate terminals of the first programmable device and the first latch device;
• a sixth latch device (58), said sixth latch device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the sixth latch device being connected to the gate terminals of the second programmable device and the second latch device;
• a first logic gate, an output of the first logic gate being connected to the gate terminals of the third and fourth latch devices;
• and
• a second logic gate, an output of the second logic gate being connected to the gate terminals of the fifth and sixth latch devices, wherein a high signal on the output of the first logic gate switches the third and fourth latch devices on and causes the first programmable device to temporarily store a logic one, and wherein a high signal on the output of the second logic gate switches the fifth and sixth latch devices on and causes the second programmable device to temporarily store a logic zero.

A programmable latch circuit for storing a value, said circuit comprising:

• a first programmable device (28), said first programmable device being a field effect transistor (FET) device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the first programmable device being connected to a reference potential;
• a second programmable device (30), said second programmable device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the second programmable device being connected to the reference potential;
• a first latch device (32), said first latch device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the first latch device being connected to the source or drain terminal of the first programmable device that is not connected to the reference potential and the other of the source or drain terminal of the first latch device being connected to a voltage source;
• a second latch device (34), said second latch device being an FET device including a source terminal, a drain terminal, and a gate terminal, one of either the source terminal or the drain terminal of the second latch device being connected to the source or drain terminal of the second programmable device that is not connected to the reference potential and the other of the source or drain terminal of the second latch device being connected to the voltage source;
• a third latch device (40), said third latch device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of a third latch device being connected to the source or drain terminal of the first programmable device that is not connected to the reference potential;
• a fourth latch device (42), said fourth latch device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the fourth latch device being connected to the source or drain terminal of the second programmable device and the other of the source or drain terminal of the fourth latch device being connected to the source or drain terminal of the second latch device that is not connected to the voltage source;
• a fifth latch device (36), said fifth latch device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the fifth latch device being connected to the gate terminals of the first latch device and the first programmable device and the other of the source or drain terminal of the fifth latch device being connected to the source or drain terminal of the fifth latch device being connected to the source or drain terminal of the second programmable device and is not connected to the reference potential;
• and
• a sixth latch device (38), said sixth latch device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the sixth latch device being connected to the gate terminals of the second latch device and the second programmable device and the other of the source or drain terminal of the sixth latch device being connected to the source or drain terminal of the first programmable device that is not connected to the reference potential, wherein input signals are applied to the latch circuit to temporarily program one of either the first programmable device or the second programmable device, and to subsequently permanently program one of the first programmable device or the second programmable device and wherein the third, fourth, fifth, and sixth latch devices are switched on under a latch condition.

A programmable latch circuit for storing a value, said circuit comprising:

• a first programmable device (28), said first programmable device being a field effect transistor (FET) device including a source terminal, a drain terminal and a gate terminal, said first programmable device further including a first capacitor in series with the gate terminal, one of either the source or drain terminal of the first programmable device being connected to a reference potential;
• a second programmable device (30), said second programmable device being an FET device including a source terminal, a drain terminal and a gate terminal, said second programmable device further including a second capacitor in series with the gate terminal, one of either the source or drain terminal of the second programmable device being connected to the reference potential;
• a first latch device (32), said first latch device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the first latch device being connected to the source or drain terminal of the first programmable device that is not connected to the reference potential and the other of the source or drain terminal of the first latch device being connected to a voltage source;
• a second latch device (34), said second latch device being an FET device including a source terminal, a drain terminal, and a gate terminal, one of either the source terminal or the drain terminal of the second latch device being connected to the source or drain terminal of the second programmable device that is not connected to the reference potential and the other of the source or drain terminal of the second latch device being connected to the voltage source;
• and
• a parity check circuit, said parity check circuit detecting a change in state of the output of the latch circuit, wherein input signals are applied to the latch circuit to temporarily program one of either the first programmable device or the second programmable device with a logical zero or a logical one, and to subsequently permanently program one of the first programmable device or the second programmable device with a logical zero or a logical one.

A programmable latch circuit for storing a value, said circuit comprising:

• a first programmable device (28), said first programmable device being a field effect transistor (FET) device including a source terminal, a drain terminal and a gate terminal, said first programmable device further including a first capacitor in series with the gate terminal, one of either the source or drain terminal of the first programmable device being connected to a reference potential;
• a second programmable device (30), said second programmable device being an FET device including a source terminal, a drain terminal and a gate terminal, said second programmable device further including a second capacitor in series with the gate terminal, one of either the source or drain terminal of the second programmable device being connected to the reference potential;
• a first latch device (32), said first latch device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the first latch device being connected to the source or drain terminal of the first programmable device that is not connected to the reference potential and the other of the source or drain terminal of the first latch device being connected to a voltage source;
• a second latch device (34), said second latch device being an FET device including a source terminal, a drain terminal, and a gate terminal, one of either the source terminal or the drain terminal of the second latch device being connected to the source or drain terminal of the second programmable device that is not connected to the reference potential and the other of the source or drain terminal of the second latch device being connected to the voltage source;
• and
• a third latch device (40) and a fourth latch device (42), both of the third and fourth latch devices being an FET device including a source terminal, a drain terminal, and a gate terminal, one of either the source or drain terminal of the third latch device being connected to the source or drain terminal of the first programmable device that is not connected to the reference potential and the other of the source or drain terminal of the third latch device being connected to the source or drain terminal of the first latch device that is not connected to the voltage source, and one of either the source or drain terminal of the fourth latch device being connected to the source or drain terminal of the second programmable device and the other of the source or drain terminal of the fourth latch device being connected to the source or drain terminal of the second latch device that is not connected to the voltage source, wherein the third and fourth latch devices are switched on during a latch condition, and wherein input signals are applied to the latch circuit to temporarily program one of either the first programmable device or the second programmable device with a logical zero or a logical one, and to subsequently permanently program one of the first programmable device or the second programmable device with a logical zero or a logical one.

A programmable latch circuit for storing a value, said circuit comprising:

• a first programmable device (28), said first programmable device being a field effect transistor (FET) device including a source terminal, a drain terminal and a gate terminal, said first programmable device further including a first capacitor in series with the gate terminal, one of either the source or drain terminal of the first programmable device being connected to a reference potential;
• a second programmable device (30), said second programmable device being an FET device including a source terminal, a drain terminal and a gate terminal, said second programmable device further including a second capacitor in series with the gate terminal, one of either the source or drain terminal of the second programmable device being connected to the reference potential;
• a first latch device (32), said first latch device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the first latch device being connected to the source or drain terminal of the first programmable device that is not connected to the reference potential and the other of the source or drain terminal of the first latch device being connected to a voltage source;
• a second latch device (34), said second latch device being an FET device including a source terminal, a drain terminal, and a gate terminal, one of either the source terminal or the drain terminal of the second latch device being connected to the source or drain terminal of the second programmable device that is not connected to the reference potential and the other of the source or drain terminal of the second latch device being connected to the voltage source;
• and
• a third latch device (36) and a fourth latch device (38), both of the third and fourth latch devices being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the third latch device being connected to the gate terminals of the first latch device and the first programmable device and the other of the source or drain terminal of the third latch device being connected to the source or drain terminal of the second programmable device that is not connected to the reference potential, and one of either the source or drain terminal of the fourth latch device being connected to the gate terminals of the second latch device and the second programmable device and the other of the source or drain terminal of the fourth latch device being connected to the source or drain terminal of the first programmable device that is not connected to the reference potential, wherein the third and fourth latch devices are switched on under a latch condition, and wherein input signals are applied to the latch circuit to temporarily program one of either the first programmable device or the second programmable device with a logical zero or a logical one, and to subsequently permanently program one of the first programmable device or the second programmable device with a logical zero or a logical one.

A programmable latch circuit for storing a value, said circuit comprising:

• a first programmable device (28), said first programmable device being a field effect transistor (FET) device including a source terminal, a drain terminal and a gate terminal, said first programmable device further including a first capacitor in series with the gate terminal, one of either the source or drain terminal of the first programmable device being connected to a reference potential;
• a second programmable device (30), said second programmable device being an FET device including a source terminal, a drain terminal and a gate terminal, said second programmable device further including a second capacitor in series with the gate terminal, one of either the source or drain terminal of the second programmable device being connected to the reference potential;
• a first latch device (32), said first latch device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the first latch device being connected to the source or drain terminal of the first programmable device that is not connected to the reference potential and the other of the source or drain terminal of the first latch device being connected to a voltage source;
• a second latch device (34), said second latch device being an FET device including a source terminal, a drain terminal, and a gate terminal, one of either the source terminal or the drain terminal of the second latch device being connected to the source or drain terminal of the second programmable device that is not connected to the reference potential and the other of the source or drain terminal of the second latch device being connected to the voltage source, wherein input signals are applied to the latch circuit to temporarily program one of either the first programmable device or the second programmable device with a logical zero or a logical one, and to subsequently permanently program one of the first programmable device or the second programmable device with a logical zero or a logical one;
• and
• a logic gate (52), a third latch device (56), and a fourth latch device (64), each of the third and fourth latch devices being an FET device including a source terminal, a drain terminal, and a gate terminal, an output of the logic gate being connected to the gate terminals of both the third and fourth latch devices, one of either the source or drain terminal of the third latch device being connected to the gate terminals of the first programmable device and the first latch device, and one of either the source or drain terminal of the fourth latch device being connected to the gate terminals of the second programmable device and the second latch device, wherein a high signal on the output of the logic gate switches the third and fourth latch devices on and causes the first programmable device to temporarily store a logical one.

A programmable latch circuit for storing a value, said circuit comprising:

• a first programmable device (28), said first programmable device being a field effect transistor (FET) device including a source terminal, a drain terminal and a gate terminal, said first programmable device further including a first capacitor in series with the gate terminal, one of either the source or drain terminal of the first programmable device being connected to a reference potential;
• a second programmable device (30), said second programmable device being an FET device including a source terminal, a drain terminal and a gate terminal, said second programmable device further including a second capacitor in series with the gate terminal, one of either the source or drain terminal of the second programmable device being connected to the reference potential;
• a first latch device (32), said first latch device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the first latch device being connected to the source or drain terminal of the first programmable device that is not connected to the reference potential and the other of the source or drain terminal of the first latch device being connected to a voltage source;
• a second latch device (34), said second latch device being an FET device including a source terminal, a drain terminal, and a gate terminal, one of either the source terminal or the drain terminal of the second latch device being connected to the source or drain terminal of the second programmable device that is not connected to the reference potential and the other of the source or drain terminal of the second latch device being connected to the voltage source, wherein input signals are applied to the latch circuit to temporarily program one of either the first programmable device or the second programmable device with a logical zero or a logical one, and to subsequently permanently program one of the first programmable device or the second programmable device with a logical zero or a logical one;
• and
• a logic gate (54), a third latch device (62), and a fourth latch device (58), each of the third and fourth latch devices being an FET device including a source terminal, a drain terminal, and a gate terminal, an output of the logic gate being connected to the gate terminals of both the third and fourth latch devices, one of either the source or drain terminal of the third latch device being connected to the gate terminals of the first programmable device and the first latch device, and one of either the source or drain terminal of the forth latch device being connected to the gate terminals of the second programmable device and the second latch device, wherein a high signal at the output of the logic gate switches the third and fourth latch devices on and causes the second programmable device to temporarily store a logical zero.

A programmable latch circuit for storing a value, said circuit comprising:

• a first programmable device (28), said first programmable device being a field effect transistor (FET) device including a source terminal, a drain terminal and a gate terminal, said first programmable device further including a first capacitor in series with the gate terminal, one of either the source or drain terminal of the first programmable device being connected to a reference potential;
• a second programmable device (30), said second programmable device being an FET device including a source terminal, a drain terminal and a gate terminal, said second programmable device further including a second capacitor in series with the gate terminal, one of either the source or drain terminal of the second programmable device being connected to the reference potential;
• a first latch device (32), said first latch device being an FET device including a source terminal, a drain terminal and a gate terminal, one of either the source or drain terminal of the first latch device being connected to the source or drain terminal of the first programmable device that is not connected to the reference potential and the other of the source or drain terminal of the first latch device being connected to a voltage source;
• a second latch device (34), said second latch device being an FET device including a source terminal, a drain terminal, and a gate terminal, one of either the source terminal or the drain terminal of the second latch device being connected to the source or drain terminal of the second programmable device that is not connected to the reference potential and the other of the source or drain terminal of the second latch device being connected to the voltage source wherein input signals are applied to the latch circuit to temporarily program one of either the first programmable device or the second programmable device with a logical zero or a logical one, and to subsequently permanently program one of the first programmable device or the second programmable device with a logical zero or a logical one;
• and
• a third latch device (46) and a fourth latch device (48), said third and fourth latch devices being an FET device including a source terminal, a drain terminal and a gate terminal, said gate terminals of each of the third and fourth latch devices being connected to a reset input, one of either the source or drain terminal of the third latch device being connected to the gate terminal of the first programmable device and the other of the source or drain terminal of the third latch device being connected to the reference potential, and one of either the source or drain terminal of the fourth latch device being connected to the gate terminal of the second programmable device and the other of the source or drain terminal of the fourth latch device being connected to the reference potential, wherein a high signal at the reset input switches the third and fourth latch devices on to clear the first and second programmable devices to provide for multiple temporary writes to the first and second programmable devices.