Low latency DRAM cell and method therefor

A memory cell, comprising:

• a first transistor having a first electrode coupled to a first read/write bitline, a second electrode coupled to a first wordline, and a third electrode;
• a second transistor having a first electrode coupled to second read/write bitline, a second electrode coupled to a second wordline, and a third electrode coupled to the third electrode of the first transistor;
• a capacitor having a first electrode coupled to the third electrode of the first transistor and a second electrode;
• and wherein;
• the first transistor selectively exchanges charge between the first bitline and the capacitor and the second bitline is substantially simultaneously precharged during a first time period, and said second transistor selectively exchanges charge between the second bitline and said first bitline is simultaneously charged during a second time period.

A method for hiding precharge a dynamic random access memory cell, comprising the steps of:

• storing a charge in a capacitor;
• selectively transferring a portion of the charge to a first output via a first previously precharged read/write conductor during a first time period using a first transfer device;
• substantially simultaneously with said step of selectively transferring the portion of the charge, precharging a second read/write conductor during the first period;
• and
• selectively transferring a portion of the charge to a second output via the precharged second read/write conductor during a second time period using a second Transfer device, wherein the first time period and the second time period are consecutive.