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US 5,856,938 AGranted
Small-sized multi-valued semiconductor memory device with coupled capacitors between divided bit lines
AssigneeNEC Corporation
InventorsNaoki Kasai, Hiroshi Watanabe, Hiroki Koga
Life of this patent
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Abstract
In a 2.sup.m (m=1, 2, . . . )-valued semiconductor memory device, including a plurality of word lines, a plurality of bit line pairs, and a plurality of memory cells each connected to one of the word lines and one bit line of the bit line pairs, each of the bit line pairs are divided into m divided bit line pairs, and a ratio of capacitances of the m divided bit line pairs is 1:2: . . . :2.sup.m-1. Also, each sense amplifier is connected to one of the bit line pairs. Further, each of coupled capacitor pairs is cross-coupled between two adjacent divided bit line pairs of the divided bit line pairs.
Claims36
A 2.sup.m (m=1, 2, . . . )-valued semiconductor memory device, comprising:
- a plurality of word lines;
- a plurality of bit line pairs each divided into m divided bit line pairs, a ratio of capacitances of said m divided bit line pairs being 1:2:
- . . . :2.sup.m-1 ;
- a plurality of memory cells each connected to one of said word lines and one bit line of said bit line pairs;
- a plurality of sense amplifiers each connected to one of said bit line pairs;
- and
- a plurality of coupled capacitor pairs each cross-coupled between two adjacent divided bit line pairs of said divided bit line pairs.
4 more elements
A 2.sup.m (m=1, 2, . . . )-valued semiconductor memory device, comprising:
- a plurality of word lines;
- a plurality of bit line pairs each divided into m divided bit line pairs, a ratio of capacitances of said m divided bit line pairs being 1:2:
- . . . :2.sup.m-1 ;
- a plurality of memory cells each connected to one of said word lines and one bit line of said bit line pairs;
- a plurality of sense amplifiers each connected to one of said bit line pairs;
- and
- a plurality of coupled capacitor pairs each cross-coupled between two adjacent divided bit line pairs of said divided bit line pairs,
- wherein each of said coupled capacitors comprises a series of capacitor units each having the same configuration as capacitors of said memory cells.
5 more elements
A four-valued semiconductor memory device, comprising:
- a plurality of word lines
- a plurality of bit line pairs each divided into first and second divided bit line pairs, each of said first and second divided bit line pairs being further divided into two sub-divided bit line pairs, capacitances of said sub-divided bit line pairs being substantially equal to each other;
- a plurality of memory cells each connected to one of said word lines and one bit line of said bit line pairs;
- a plurality of sense amplifiers each connected to one of said sub-divided bit line pairs of said first and second bit line pairs on a center side of said device;
- and
- a plurality of coupled capacitor pairs each cross-coupled between said first and second divided bit line pairs,
- said sub-divided bit line pairs of said first divided bit line pair being electrically separated to each other when a memory cell of said memory cells connected to said second divided bit line pair is accessed,
- said sub-divided bit line pairs of said second divided bit line pair being electrically separated from each other when a memory cell of said memory cells connected to said first divided bit line pair is accessed.
5 more elements
A four-valued semiconductor memory device, comprising:
- a plurality of word lines
- a plurality of bit line pairs each divided into first and second divided bit line pairs, each of said first and second divided bit line pairs being further divided into two sub-divided bit line pairs, capacitances of said sub-divided bit line pairs, being substantially equal to each other;
- a plurality of memory cells each connected to one of said word lines and one bit line of said bit line pairs;
- a plurality of sense amplifiers each connected to one of said sub-divided bit line pairs of said first and second bit line Pairs on a center side of said device;
- and
- a plurality of coupled capacitor pairs each cross-coupled between said first and second divided bit line pairs,
- said sub-divided bit line pairs of said first divided bit line pair being electrically separated to each other when a memory cell of said memory cells connected to said second divided bit line pair is accessed,
- said sub-divided bit line pairs of said second divided bit line pair being electrically separated from each other when a memory cell of said memory cells connected to said first divided bit line pair is accessed;
- wherein each of said coupled capacitors comprises a series of capacitor units each having the same configuration as capacitors of said memory cells.
6 more elements
A semiconductor device comprising:
- first, second, third and fourth connection lines;
- a first switching element connected between said first and second connection lines and controlled by a first control signal;
- a second switching element connected between said third and fourth connection lines and controlled by said first control signal;
- a first capacitor connected between said first and fourth connection lines;
- a second capacitor connected between said second and third connection lines;
- a first comparator, connected to said first and third connection lines, for comparing a voltage at said first connection line with a voltage at said third connection line to increase a difference between the voltages at said first and third connection lines, in response to a second control signal;
- a second comparator, connected to said second and fourth connection lines, for comparing a voltage at said second connection Line with a voltage at said fourth connection line to increase a difference between the voltages at said second and fourth connection lines in response to a third control signal.
4 more elements
A semiconductor device comprising:
- first, second, third, fourth, fifth, sixth, seventh and eighth connection lines;
- a first switching element connected between said second and third connection lines and controlled by a first control signal;
- a second switching element connected between said sixth and seventh connection lines and controlled by said first control signal;
- a third switching element connected between said first and second connection lines and controlled by a second control signal;
- a fourth switching element connected between said fifth and sixth connection lines and controlled by said second control signal;
- a fifth switching element connected between said third and fourth connection lines and controlled by a third control signal;
- a sixth switching element connected between said seventh and eighth connection lines and controlled by said third control signal;
- a first capacitor connected between said second and seventh connection lines;
- a second capacitor connected between said third and sixth connection lines;
- a first comparator, connected to said second and sixth connection lines, for comparing a voltage at said second connection Line with a voltage at said sixth connection line to increase a difference between the voltages at said second and sixth connection lines in response to a fourth control signal;
- a second comparator, connected to said third and seventh connection lines, for comparing a voltage at said third connection line with a voltage at said seventh connection line to increase a difference between the voltages at said third and sixth connection lines, in response to a fifth control signal.
8 more elements
Dependencies are inferred from the claim text.