Calculating A - sign(A) in a single instruction cycle
AssigneeSamsung Semiconductor, Inc.
InventorRoney S. Wong
Life of this patent
Estimating the term…
Abstract
The expression A-sign(A), where A is a signed binary integer represented in 2's complement form, sign (A) is equal to one when A is greater than zero, sign (A) is equal to zero when A is zero, and sign (A) is equal to negative one when A is less than zero, is calculated by bit-complementingA, bit-complementing (A-1) when A is less than zero, bit-complementing A when A is equal to zero, and bit-complementing (A+1) when A is greater than zero. Zero detect for A is provided by determining whether a first carry-out bit from (A+0) and a second carry-out bit from (A+1) have different logical values. In this manner, A-sign (A) can be calculated by a general purpose computer in a single instruction cycle.
Claims11
An apparatus for calculating A-sign (A), where A is a signed binary integer represented in 2's complement form, sign (A) is equal to one when A is greater than zero, sign (A) is equal to zero when A is zero, and sign (A) is equal to negative one when A is less than zero comprising:
- a first inverter circuit for bit-complementing A to obtain A;
- a data selector circuit for setting a constant C to negative one when A is less than zero and for setting the constant C to zero when A is greater than or equal to zero;
- an adder circuit for calculating (A-1) at a sum output when A is less than zero, for calculating (A+0) at the sum output when A is zero, and for calculating (A+1) at a sum-plus-one output when A is greater than zero;
- a multiplexer for selecting between the sum output and the sum-plus-one output;
- and
- a second inverter circuit for bit-complementing an output of the multiplexer, wherein an output of the second inverter circuit provides A-sign (A).
An apparatus for calculating A-sign (A), where A is a signed binary integer represented in 2's complement form, sign (A) is equal to one when A is greater than zero, sign (A) is equal to zero when A is zero, and sign (A) is equal to negative one when A is less than zero, comprising:
- a first inverter circuit having an operand input coupled to A and having an output for providing a bit-complement of A;
- a data selector circuit having an input coupled to a sign bit of A and having an output for setting a constant C to zero when A is greater than or equal to zero and for setting the constant C to negative one when A is less than zero;
- an adder circuit having a first operand input coupled to the output of the first inverter circuit, having a second operand input coupled to the output of the data selector circuit, having a sum output representing a sum of the first and second operands, and having a sum-plus-one output representing a sum of the first and second operands plus one;
- a zero detect circuit for determining whether A is zero or nonzero;
- a multiplexer having a first input coupled to the sum output, having a second input coupled to the sum-plus-one output, having a select input, and having an output;
- a control circuit, responsive to a sign bit of A and the zero detect circuit, having a control output coupled to the select input of the multiplexer, which causes the multiplexer to select the first input thereof when A is less than or equal to zero, and causes the multiplexer to select the second input thereof when A is greater than zero;
- and
- a second inverter circuit having an operand input coupled to the output of the multiplexer, and having an output that provides A-sign (A).
Dependencies are inferred from the claim text.