System and method for digital simulation of an electrical circuit

A method of simulating an electric circuit having connections between logical gates and gate arrangements, said method comprising the steps of:

• (a) classifying connections between any two of the group consisting of AND, NAND, OR, and NOR gates as either homogeneous connections or heterogeneous connections;
• said homogeneous connections being characterized as a connection between two AND gates, between two OR gates, from an AND gate to a NAND gate, from an OR gate to a NOR gate, from a NAND gate to an OR gate, from a NAND gate to a NOR gate, from a NOR gate to an AND gate, or from a NOR gate to a NAND gate, and said heterogeneous connections being characterized as a connection between two NAND gates, between two NOR gates, from an AND gate to an OR gate, from an AND gate to a NOR gate, from an OR gate to an AND gate, from an OR gate to a NAND gate, from a NAND gate to an AND gate, or from a NOR gate to an OR gate;
• (b) removing all NOT gates from the circuit;
• (c) collapsing all homogeneous connections that do not fan out to more than one gate, including at least one connection from a NAND gate to an OR gate, from a NAND gate to a NOR gate, from a NOR gate to an AND gate, or from a NOR gate to a NAND gate;
• and
• (d) collapsing at least one of said heterogeneous connections.

A method of simulating an electric circuit having connections between logical gates and gate arrangements, wherein said method has an event processing phase, said method comprising the steps of:

• (a) classifying connections between any two of the group consisting of AND, NAND, OR, and NOR gates as either homogeneous connections or heterogeneous connections;
• said homogeneous connections being characterized as a connection between two AND gates, between two OR gates, from an AND gate to a NAND gate, from an OR gate to a NOR gate, from a NAND gate to an OR gate, from a NAND gate to a NOR gate, from a NOR gate to an AND gate, or from a NOR gate to a NAND gate;
• and
• said heterogeneous connections being characterized as a connection between two NAND gates, between two NOR gates, from an AND gate to an OR gate, from an AND gate to a NOR gate, from an OR gate to an AND gate, from an OR gate to a NAND gate, from a NAND gate to an AND gate, or from a NOR gate to an OR gate;
• (b) removing all NOT gates from the circuit;
• (c) collapsing all homogeneous connections that do not fan out to more than one gate, including at least one connection from a NAND gate to an OR gate, from a NAND gate to a NOR gate, from a NOR gate to an AND gate, or from a NOR gate to a NAND gate;
• (d) collapsing at least one of said heterogeneous connections that do not fan out to more than one gate;
• (e) creating multi-level collapsed connections;
• (f) eliminating all net values, except those net values that are visible to a user;
• (g) scheduling the simulation of only those gates and gate arrangements of the circuit whose outputs will change value during the simulation;
• (h) simulating gates only by inverting their output either from a logical ONE to a logical ZERO or from a logical ZERO to a logical ONE;
• (i) block scheduling fanout branches;
• and
• (j) executing a counting routine during the event processing phase rather than a gate simulation phase;
• and
• wherein said method includes event driven processing and wherein an event corresponds to a change in a single fanout branch of a net.