Logic synthesis method and system with intermediate circuit files

An incremental logic synthesis method for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising the steps of:

• inputting an old logic file, an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction, and a new logic file partially changed from said old logic file;
• generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file;
• updating by discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit;
• and
• optimizing by generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit, and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction,
• wherein said updating step comprises the steps of:
• discriminating a corresponding flip-flop pair by discriminating a pair of flip flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit, and
• comparing the function of a cone having a gate combinational circuit with one output in said old circuit with the function of a cone having a gate combinational circuit with one output in said first intermediate circuit, selecting a circuit containing at least one gate in a cone of said old circuit with an equivalent logic function, as said common sub-circuit, and selecting a circuit containing a gate in a cone of said first intermediate circuit with an inconsistent logic function and a circuit containing a gate in a cone not identified as the comparison object, as said uncommon sub-circuit.

An incremental logic synthesis system for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising:

• an old logic file;
• an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction;
• logic capture means for inputting a new logic file partially changing from said old logic file;
• logic synthesizing means for generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file;
• circuit updating means for discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit file;
• and
• circuit optimizing means for generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction,
• wherein said circuit updating means comprises:
• corresponding flip-flop pair discriminating means for discriminating a pair of flip-flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit, and
• duplicate circuit deleting means for deleting a duplicate circuit contained both in said common sub-circuit of said old circuit file and in said uncommon sub-circuit of said first intermediate circuit file, from said first intermediate circuit, in accordance with an output from said corresponding flip-flop pair discriminating means.

An incremental logic synthesis system for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising:

• an old logic file;
• an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction;
• logic capture means for inputting a new logic file partially changing from said old logic file;
• logic synthesizing means for generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file;
• circuit updating means for discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit file;
• and
• circuit optimizing means for generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction,
• wherein said circuit updating means comprises:
• corresponding flip-flop pair discriminating means for discriminating a pair of flip-flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit, and
• wherein said circuit optimizing means generates said second intermediate circuit file by merging said common sub-circuit of said old circuit file, said uncommon sub-circuit of said first intermediate circuit file, flip-flops in said first intermediate circuit, and primary input/output terminals of said first intermediate circuit of said first intermediate circuit file.

An incremental logic synthesis method for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising the steps of:

• inputting an old logic file, an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction, and a new logic file partially changed from said old logic file;
• generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file;
• updating by discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit;
• and
• optimizing by generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit, and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction;
• wherein said updating step comprises the steps of:
• discriminating a corresponding flip-flop pair by discriminating a pair of flip flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit, and
• deleting a duplicate circuit contained both in said common sub-circuit of said old circuit file and in said uncommon sub-circuit of said first intermediate circuit file, from said first intermediate circuit, in accordance with an output from said corresponding discriminating step.

An incremental logic synthesis method for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising the steps of:

• inputting an old logic file, an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction, and a new logic file partially changing from said old logic file;
• generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file;
• updating by discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit;
• and
• optimizing by generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit, and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction;
• wherein said updating step comprises the step of:
• discriminating a corresponding flip-flop pair by discriminating a pair of flip flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit;
• and
• wherein said circuit optimizing step comprises the step of:
• generating said second intermediate circuit file by merging said common sub-circuit of said old circuit file, said uncommon sub-circuit of said first intermediate circuit file, flip-flops in said first intermediate circuit, and primary input/output terminals of said first intermediate circuit of said first intermediate circuit file.