Apparatus and method for intermodular communications using system bus controllers

In a system bus architecture having a backplane bus with a shared memory unit controlled by a plurality of registers, a master module, having a master bus controller and a master central processing unit, and at least one slave module, having a slave bus controller and a slave central processing unit, a method of master-slave module communications, comprising:

• requesting access, by said master central processing unit, to the bus;
• determining, by said master central processing unit, whether the bus can be accessed;
• receiving acknowledgment, by said master central processing unit, that the bus can be accessed;
• accessing the shared memory, by said master central processing unit, to transfer data between said master and slave modules;
• indicating to the master bus controller, by the master central processing unit, that said data transfer is complete;
• indicating to the slave module, by said master bus controller, that said transferred data is in the shared memory;
• accessing the shared memory, by said slave central processing unit, to read said transferred data;
• and
• indicating to the slave bus controller, by said slave central processing unit, that said data read is complete.

In a system bus architecture having a backplane bus with a shared memory unit controlled by a plurality of registers, a master module, having a master bus controller and a master central processing unit, and at least one slave module, having a slave bus controller and a slave central processing unit, a method of slave-master module communications comprising:

• requesting access, by said slave central processing unit, to the bus;
• determining, by said slave central processing unit, whether the bus can be accessed;
• receiving acknowledgment, by said slave central processing unit, that the bus can be accessed;
• accessing the shared memory, by said slave central processing unit, to transfer data between said slave and master modules;
• indicating to the slave bus controller, by the slave central processing unit, that said data transfer is complete;
• indicating to the master module, by said slave bus controller, that said transferred data is in said shared memory;
• accessing the shared memory, by said master central processing unit, to read said transferred data;
• and
• indicating to the master bus controller, by said master central processing unit, that said data read is complete.