Internal power supply circuit
AssigneeSony Corporation
InventorsMitsuo Soneda, Akira Li
Life of this patent
Estimating the term…
Abstract
An internal power supply circuit, comprising a plurality of charge accumulators, a first power supply terminal, a second power supply terminal, a first switch for connecting the plurality of charge accumulators in parallel to each other in a first state, and a second switch for connecting the plurality of charge accumulators in series with each other in a second state, the charge accumulators connected between the first power supply terminal and the second power supply terminal at either the first state or the second state, and the first state and the second state set repeatedly to raise or lower a voltage between the first power supply terminal and the second power supply terminal.
Claims38
An internal power supply circuit, comprising;
- a plurality of charge accumulating means,
- an input power supply terminal,
- a boasted voltage output terminal,
- a first switching means for connecting the plurality of charge accumulating means in parallel to each other in a first state,
- a second switching means for connecting the plurality of charge accumulating means in series with each other in a second state,
- wherein the first switching means comprises a third switching means and a fourth switching means, said third switching means connecting said charge accumulating means to a voltage supply line, and said fourth switching means connecting said charge accumulating means to ground;
- and
- a control means for energizing the first switching means or the second switching means in response to the first state or the second state to connect the plurality of charge accumulating means between the first power supply terminal and the second power supply terminal, and for deenergizing the first switching means or the second switching means in response to the first state or the second state to disconnect the plurality of charge accumulating means between the first power supply terminal and the second power supply terminal, the control means repeating the energizing and the deenergizing,
- a plurality of partial booster circuits each comprising one of said charge accumulating means connected between a first node and a second node,
- wherein the second switching means holds in a non-conductive state the first node of a first partial booster circuit and the second node of a rear partial booster circuit in the first state and in a conductive state in the second state;
- further wherein the third switching means and the fourth switching means are held in the conductive state and the second switching means is held in a non-conductive state in the first state;
- and
- further wherein the first switching means comprised of the third switching means and the fourth switching means is held in the non-conductive state and the second switching means is held in a conductive state in the second state so as to raise the voltage between the input terminal and the output terminal.
An internal power supply circuit for boosting voltage comprising:
- a plurality of charge storing devices;
- a first plurality of transistors connected alternately and in series with said plurality of charge storing devices, wherein said series begins with a first transistor of said first plurality of transistors and ends with a last transistor of said first plurality of transistors;
- a second plurality of transistors each of which is connected between a voltage supply line and a connection point between one of said plurality of charge storing devices and one of said first plurality of transistors;
- and
- a third plurality of transistors each of which is connected between ground and a connection point between one of said plurality of charge storing devices and one of said first plurality of transistors;
- wherein a gate of each of said first plurality of transistors, excluding said last transistor, is connected to a first clock line supplying a first clock signal;
- further wherein a gate of each of said second plurality of transistors is connected to a second clock line supplying a second clock signal, different from said first clock signal;
- and
- further wherein a gate of each of said third plurality of transistors is connected to a third clock line supplying a third clock signal, different from said second clock signal.
Dependencies are inferred from the claim text.