US 5,856,891 A · MR resistive-biasing scheme providing low noise high common-mode rejection and high supply rejection

Abstract

The present invention is a system for reading information stored on a plurality of disk surfaces. The system comprises a plurality of channels each containing a preamplifier having first and second terminals for connection to an MR head. A bias circuit is provided common to all of the plurality of channels. The preamplifier in each channel includes first and second channel select circuits responsive to first and second channel select signals and current output from the bias circuit to output currents based on the current's output from the bias circuit. The preamplifier in each channel also includes first and second complementary output transistor circuits responsive to the current's output from the first and second channel select circuits and to the first and second voltages to provide bias current through the respective MR head connected between the first and second terminals of the respective channel. The system is entirely symmetrical around ground for improved common mode rejection. In another aspect of the system, first and second supply rejection circuits are provided to stabilize voltages at the first and second terminals for variations in the positive and negative power supplies.

Claims32

Dependent claims

A system for reading information stored on a plurality of disk surfaces, the system comprising a plurality of channels each containing a preamplifier having first and second terminals for connection to an MR head associated with a respective disk surface, the preamplifier providing a bias current to the respective MR head, a supply circuit symmetrically arranged around ground to provide first and second voltages having equal amplitudes and opposite polarities, the preamplifier in each channel comprising:

a first channel select circuit responsive to a first channel select signal;
a second channel select circuit, arranged symmetrically around ground to the first channel select circuit, responsive to a second channel select signal;
and
first and second complementary output transistor circuits, the second output transistor circuit being symmetrical around ground to the first output transistor circuit, the first output transistor circuit being responsive to the first channel select circuit and the first voltage to provide a first bias current to the respective first terminal, the second output transistor being responsive to the second channel select circuit and the second voltage to provide a second bias current to the respective second terminal, the first and second bias currents being based on the first and second voltages.

1 more element

A system for reading information stored on a disk surface, the system including first and second terminals for connection to an MR head associated with the disk surface, means for connection to positive and negative power supplies, and a preamplifing circuit comprising:

a supply circuit providing first and second voltages having equal amplitudes and opposite polarities, the first and second voltages being symmetrical around ground;
first and second complementary output transistor circuits, the second output transistor circuit being symmetrical around ground to the first output transistor circuit, the first output transistor circuit being responsive to the first voltage to provide a first bias current to the first terminal, the second output transistor circuit being responsive to the second voltage to provide a second bias current to the second terminal, the first and second bias currents being based on the first and second voltages.

A circuit for deriving a bias current for a plurality of channels, each channel including first and second terminals for connection to a respective MR head, the circuit comprising:

a first voltage bus connected to each of the channels to supply a first voltage to each channel, and
a second voltage bus connected to each of the channels to supply a second voltage to each channel, the first and second voltages having equal amplitudes and opposite polarities;
and
each channel including
a first resistor connected between the first voltage bus and the respective first terminal to provide a first current, and
a second resistor connected between the second voltage bus and the respective second terminal to provide a second current, the first and second currents having equal magnitudes and opposite directions so that the first and second currents flow through the MR head in the same direction.

3 more elements

Dependencies are inferred from the claim text.

MR resistive-biasing scheme providing low noise high common-mode rejection and high supply rejection

Life of this patent

MR resistive-biasing scheme providing low noise high common-mode rejection and high supply rejection

Life of this patent

Abstract

Claims32