US 5,856,851 AGranted

Clock phase synchronizing circuit

AssigneeNEC Corporation

InventorHideo Makita

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Abstract

When the margin between a write frequency-divided clock signal and a read frequency-divided clock signal becomes remarkably decreased, a clock phase difference detecting circuit outputs a reset execution command. While a reset execution command is being output in a blanking interval, a reset signal generating circuit supplies a reset signal to an input side counter corresponding to a reset execution command so as to reset the phase of the write frequency-divided clock signal to an initial state.

Claims8

Dependent claims

A clock phase synchronizing circuit, comprising:

a picture signal input terminal for receiving a serial digital picture signal;
a picture signal output terminal;
an input clock input terminal for receiving an input clock signal in synchronization with data of the picture signal received by said picture signal input terminal;
an output clock input terminal for receiving an output clock signal;
a timing reference signal input terminal for receiving a black burst signal of the picture signal;
a register composed of N flip-flops connected in parallel, wherein N is an integer greater than one, for temporarily storing data supplied from said picture signal input terminal and outputting the data as output signals;
an input side counter for receiving the input clock signal from said input clock input terminal, generating N write frequency-divided clock signals with phases that differ by one clock period, and supplying the write frequency-divided clock signals to the relevant flip-flops as write clock signals;
an output side counter for receiving an output clock signal from said output clock input terminal, generating N read frequency-divided clock signals with phases that differ by one clock period, and outputting the N read frequency-divided clock signals as selection signals;
a selection output circuit for receiving the selection signals, selecting one of the output signals of the flip-flops corresponding to the selection signals, and outputting the selected output signal to said picture signal output terminal;
a clock phase difference detecting circuit for detecting the phase difference of a read frequency-divided clock signal and a relevant write frequency-divided clock signal corresponding to a selected flip-flop and outputting a reset execution command when the phase difference is no greater than a predetermined value;
a reset timing signal generating circuit for detecting a blanking interval from the black burst signal received from said timing reference signal input terminal and outputting a reset timing signal in the blanking interval;
and
a reset signal generating circuit for receiving the reset timing signal and outputting a reset signal to said input side counter such that said input side counter forcedly resets the phases of the write frequency-divided clock signals to an initial state in accordance with the reset timing signal when the reset execution command is output.

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Dependencies are inferred from the claim text.

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Abstract

A clock phase synchronizing circuit, comprising:

a picture signal input terminal for receiving a serial digital picture signal;
a picture signal output terminal;
an input clock input terminal for receiving an input clock signal in synchronization with data of the picture signal received by said picture signal input terminal;
an output clock input terminal for receiving an output clock signal;
a timing reference signal input terminal for receiving a black burst signal of the picture signal;
a register composed of N flip-flops connected in parallel, wherein N is an integer greater than one, for temporarily storing data supplied from said picture signal input terminal and outputting the data as output signals;
an input side counter for receiving the input clock signal from said input clock input terminal, generating N write frequency-divided clock signals with phases that differ by one clock period, and supplying the write frequency-divided clock signals to the relevant flip-flops as write clock signals;
an output side counter for receiving an output clock signal from said output clock input terminal, generating N read frequency-divided clock signals with phases that differ by one clock period, and outputting the N read frequency-divided clock signals as selection signals;
a selection output circuit for receiving the selection signals, selecting one of the output signals of the flip-flops corresponding to the selection signals, and outputting the selected output signal to said picture signal output terminal;
a clock phase difference detecting circuit for detecting the phase difference of a read frequency-divided clock signal and a relevant write frequency-divided clock signal corresponding to a selected flip-flop and outputting a reset execution command when the phase difference is no greater than a predetermined value;
a reset timing signal generating circuit for detecting a blanking interval from the black burst signal received from said timing reference signal input terminal and outputting a reset timing signal in the blanking interval;
and
a reset signal generating circuit for receiving the reset timing signal and outputting a reset signal to said input side counter such that said input side counter forcedly resets the phases of the write frequency-divided clock signals to an initial state in accordance with the reset timing signal when the reset execution command is output.

10 more elements