US 5,856,818 AGranted

Timing control device for liquid crystal display

AssigneeSamsung Electronics Co., Ltd.

InventorsJeong-Min Oh, Hyueog-Sang Shin

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Abstract

A timing control device for liquid crystal display including odd data driver ICs and even data driver ICs, both group of ICs being arrayed serially on one part of the liquid crystal display panel, color signals being converted to appear alternately at the odd data and the even-data according to a number of channels of driver IC, the odd data and the even data being transmitted to the odd data driver ICs and the even data driver ICs respectively, each one of the odd data driver ICs and the even data driver ICs simultaneously operating the liquid crystal display, effecting driver frequency to be reduced, the color signal being similar type to a single bank type, enabling the data driver ICs to be arranged on one face of the liquid crystal display panel, effecting compact design of the data driver ICs.

Claims24

Dependent claims

A timing control device for liquid crystal display, comprising:

a control signal processor for generating a control signal for a gate driver and a data driver of liquid crystal display after receiving a vertical synchronizing signal, horizontal synchronizing signal and a main clock signal;
a sequential signal generator for generating a latch clock signal and a sequential control signal after receiving the main clock signal and a data enable signal;
a plurality of shift blocks for shifting sequentially an odd data and an even data of a dual bank color signal in response to the main clock signal and for outputting them;
a plurality of latch blocks for outputting simultaneously n number of odd data and n number of even data outputted from the shift blocks in response to the latch control signal;
a plurality of first composite blocks for generating an odd component of color signal by logical AND functions of n/2 number of odd data and n/2 number of even data outputted from the latch blocks with the sequential control signals in an alternative mode and then by logical OR functions of the result of the logical AND functions;
and
a plurality of second composite blocks for generating an odd component of color signal by logical AND functions of the remaining n/2 number of odd data and the remaining n/2 number of even data outputted from the latch blocks with the sequential control signals in an alternative mode and then by logical OR functions of the result of the logical AND functions.

4 more elements

A liquid crystal display, comprising:

a control signal processor for generating a control signal to control a gate driver and a data driver of liquid crystal display after receiving a vertical synchronizing signal, a horizontal synchronizing signal and a main clock signal;
a sequential signal generator for generating a latch clock signal and a sequential control signal after receiving a main clock signal and a data enable signal;
a plurality of shift blocks for shifting sequentially an odd data and an even data of a dual bank color signal in accordance with the main clock signal and for outputting them;
a plurality of latch blocks for outputting simultaneously n number of odd data and n number of even data which are outputted from the shift blocks in accordance with the latch clock signal;
a plurality of first composite blocks for generating an odd component of color signal by logical AND functions of n/2 number of odd data and n/2 number of even data outputted from the latch blocks with the sequential control signals in an alternative mode and then by logical OR functions of the result of the logical AND functions;
a plurality of second composite blocks for generating an odd component of color signal by logical AND functions of the remaining n/2 number of odd data and the remaining n/2 number of even data outputted from the latch blocks with the sequential control signals in an alternative mode and then by logical OR functions of the result of the logical AND functions;
a plurality of odd data driver ICs, each having n number of channels, for generating a liquid crystal drive signal after receiving the odd component of color signal outputted from the plurality of first composite blocks;
a plurality of even data driver ICs, each having n number of channels, for generating a liquid crystal drive signal after receiving the even component of color signal outputted from the plurality of second composite blocks;
and
a liquid crystal display panel which operates in response to a liquid crystal display drive signal inputted from the plurality of data driver ICs, said plurality of odd data driver ICs and said plurality of even data driver ICs being arranged serially on one part of the liquid crystal display panel.

7 more elements

A timing control device for liquid crystal display, comprising:

a control signal processor for generating a latch clock signal, a half frequency clock signal obtained by dividing a main clock signal and a control signal for a gate driver and a data driver for liquid crystal display after receiving a vertical synchronizing signal, a horizontal synchronizing signal and a main colck signal;
a sequential signal generator for generating a sequential control signal from a data enable signal and the half frequency clock signal;
a plurality of shift blocks for shifting color signal data sequentially according to the main clock signal after receiving a single bank color signal and for outputting them;
a plurality of latch blocks for dividing every n unmber of color data outputted from the shift blocks and for outputting 2n number of color data in response to the latch clock signal;
a first composite block for generating an odd component of a color signal by logical AND functions of n data from the latch block with the sequential control signals in a serial mode and then by logical OR functions of the result of the logical AND functions;
and
a second composite block for generating an even component of a color signal by logical AND functions of the remaining n data from the latch block with the sequential control signals in a serial mode and then by logical OR functions of the result of the logical AND functions.

4 more elements

A liquid crystal display, comprising:

a control signal processor for generating a latch clock signal, a half frequency signal obtained by dividing a main clock signal and a control signal for a gate driver and a data driver for liquid crystal display after receiving a vertical synchronizing signal, a horizontal synchronizing signal and a main colck signal;
a sequential signal generator for generating a sequential control signal from a data enable signal and the half frequency clock signal;
a plurality of shift blocks for shifting color signal data sequentially according to the main clock signal after receiving a single bank color signal and for outputting them;
a plurality of latch blocks for dividing every n unmber of color data outputted from the shift blocks and for outputting 2n number of color data in response to the latch clock signal;
a first composite block for generating an odd component of a color signal by logical AND functions of n number of data from the latch block with the sequential control signals sequentially and then by logical OR functions of the result of the logical AND functions;
a second composite block for generating an even component of a color signal by logical AND functions of the remaining n number of data from the latch block with the sequential control signals sequentially and then by logical OR functions of the result of the logical AND functions;
a plurality of odd data driver ICs, each having n number of channels, for generating a liquid crystal display drive signal after receiving an odd component of a color signal from the first composite blocks;
a plurality of even data driver ICs, each having n number of channels, for generating a liquid crystal display drive signal after receiving an even component of a color signal from the plurality of second composite blocks;
and
a liquid crystal display panel which operates in response to a liquid crystal display drive signal inputted from the plurality of data driver ICs, said plurality of odd data driver ICs and said plurality of even data driver ICs being arranged serially on one part of the liquid crystal display panel.

7 more elements

A timing control device for liquid crystal display, comprising:

a control signal processor for generating a latch clock signal, a half frequency clock signal obtained by dividing a main clock signal and a control signal for a gate driver and a data driver for liquid crystal display after receiving a vertical synchronizing signal, a horizontal synchronizing signal and a main colck signal;
a sequential signal generator for generating n number of latch control signals within every n clock pulses of the main clock signal and n number of sequential control signals within every n clock pulses of the half frequency clock signal after receiving a main clock signal, a half frequency clock signal and a data enable signal, each of n number of latch control signals having a high level duration equal to one pulse duration of the main clock signal and each of n number of sequential control signals having a high level duration equal to one clock pulse duration of the half frequency clock signal;
a plurality of latch blocks, after receiving a single bank color signal and the latch control signal, for outputting sequentially data of the single bank color signal in the high level duration of the latch control signal, and for sustaining the output state until a next high duration of the latch control signal is inputted;
a plurality of first composite blocks for generating an odd component of a color signal during the sustaining period by logical AND functions of color signal data from the latch block with the sequential control signals in a serial mode and then by logical OR functions of the result of the logical AND functions;
and
a plurality of second composite blocks for generating an even component of a color signal during the sustaining period by logical AND functions of color signal data from the latch block with the sequential control signals of rearranged sequence and then by logical OR functions of the result of the logical AND functions.

3 more elements

A liquid crystal display, comprising:

a control signal processor for generating a latch clock signal, a half frequency clock signal obtained by dividing a main clock signal and a control signal for a gate driver and a data driver for liquid crystal display after receiving a vertical synchronizing signal, a horizontal synchronizing signal and a main colck signal;
a sequential signal generator for generating n number of latch control signals within every n clock pulses of the main clock signal and n number of sequential control signals within every n clock pulses of the half frequency clock signal after receiving a main clock signal, a half frequency clock signal and a data enable signal, each of n number of latch control signals having a high level duration equal to one pulse duration of the main clock signal and each of n number of sequential control signals having a high level duration equal to one clock pulse duration of the half frequency clock signal;
a plurality of latch blocks, after receiving a single bank color signal and the latch control signal, for outputting sequentially data of the single bank color signal in the high level duration of the latch control signal, and for sustaining the output state until a next high duration of the latch control signal is inputted;
a plurality of first composite blocks for generating an odd component of a color signal during the sustaining period by logical AND functions of color signal data from the latch block with the sequential control signals in a serial mode and then by logical OR functions of the result of the logical AND functions;
a plurality of second composite blocks for generating an even component of a color signal during the sustaining period by logical AND functions of color signal data from the latch block with the sequential control signals of rearranged sequence and then by logical OR functions of the result of the logical AND functions;
a plurality of odd data driver ICs, each having n number of channels, for generating a liquid crystal display drive signal after receiving an odd component of a color signal from the first composite blocks;
a plurality of even data driver ICs, each having n number of channels, for generating a liquid crystal display drive signal after receiving an even component of a color signal from the plurality of second composite blocks;
and
a liquid crystal display panel which operates in response to a liquid crystal display drive signal inputted from the plurality of data driver ICs, said plurality of odd data driver ICs and said plurality of even data driver ICs being arranged serially on one part of the liquid crystal display panel.

6 more elements

A timing control device for liquid crystal display, comprising:

a control signal processor for generating a latch clock signal, a half frequency clock signal obtained by dividing a main clock signal and a control signal for a gate driver and a data driver for liquid crystal display after receiving a vertical synchronizing signal, a horizontal synchronizing signal and a main colck signal;
a data frequency divider for converting the single bank color signal to a dual bank color signal according to the half frequence clock signal when an input color signal from external selection signal is single bank, and for outputting the color signal without converting when an input color signal from external selection signal is dual bank;
a plurality of latch pulse generator, after receiving a data enable signal and a half frequency clock signal, for generating a first sequential control signal and a second sequential control signal from the data enable signal and the half frequency clock signal, for generating a latch control signal by performing a logical OR function of more than two of the first sequential control signal, and for generating an adding control signal by performing a logical OR function of more than two of the second sequential control signal;
and
a plurality of data processing cells for latching an odd data and an even data outputted from the data frequency divider according to the latch control signal, and for generating an odd component and an even component of color signal by performing a logical operation between the latched data and the adding control signal, said latch control signal and adding control signal being predetermined so that a data of color signal appears alternately in the odd component and the even component as much as the channel number of data driver IC, said odd component being inputted to odd numbered data driver IC of a data driver and said even component being inputted to even numbered data driver IC of a data driver.

2 more elements

A liquid crystal display, comprising:

a control signal processor for generating a latch clock signal, a half frequency clock signal obtained by dividing a main clock signal and a control signal for a gate driver and a data driver for liquid crystal display after receiving a vertical synchronizing signal, a horizontal synchronizing signal and a main colck signal;
a data frequency divider for converting the single bank color signal to a dual bank color signal according to the half frequency clock signal when a color signal from an external selecting signal is a single bank, and for outputting the color signal without a converting step when a color signal from an external selecting signal is a dual bank;
a plurality of latch pulse generators for generating a first sequential control signal and a second sequential control signal from the data enable signal and the half frequency clock signal after receiving the data enable signal and the half frequency clock signal, for generating a latch control signal by a logical OR function of more than two of the first sequential control signals, and for generating an adding control signal by a logical OR function of more than two of the second sequential control signals;
a plurality of data processing cells for generating an odd component and an even component of the color signal after latching an odd data and an even data of the dual bank color signal outputted from the data frequency divider and then carrying out a logical function between the latched data and the adding control signal;
a plurality of odd data driver ICs, each having n number of channels, for generating a liquid crystal display drive signal after receiving an odd component of a color signal from the first composite blocks;
a plurality of even data driver ICs, each having n number of channels, for generating a liquid crystal display drive signal after receiving an even component of a color signal from the plurality of second composite blocks;
and
a liquid crystal display panel which operates in response to a liquid crystal display drive signal inputted from the plurality of data driver ICs, said plurality of odd data driver ICs and said plurality of even data driver ICs being arranged serially on one part of the liquid crystal display panel.

5 more elements

Dependencies are inferred from the claim text.