Data driver for liquid crystal display

A data driver for a liquid crystal display comprising:

• a first signal generating circuit for externally producing a source start signal;
• a second signal generating circuit for externally producing a first clock signal;
• a third signal generating circuit for externally producing a load signal;
• a fourth signal generating circuit for externally producing a polarity signal;
• and
• a single integrated circuit including:
• an m-bit register circuit for shifting the source start signal corresponding to the first clock signal and outputting a latch clock signal, where m is an integer;
• a data latch circuit for latching and outputting a first set of three video signals of odd data and a second set of three video signals of even data, the data latch circuit receiving all of the video signals simultaneously, each set representing a pixel in the liquid crystal display, each of the video signals having n-bits of data, where n is an integer;
• a 3m.times.n line latch circuit including a first latch unit and a second latch unit for latching the video signals from the data latch circuit corresponding to the latch clock signal from the shift register, the line latch circuit storing and outputting the video signals according to the load signal of the third signal generation circuit, the first latch unit including first and second odd line latches and the second latch unit including first and second even line latches, the first odd line latch receiving the first set of the three video signals and the first even line latch receiving the second set of the three video signals, wherein one horizontal line of display data stored in the first odd and even line latches is stored in the second odd and even line latches in response to the load signal;
• a polarity inversion circuit for inverting a polarity of the video signals from the data latch circuit;
• and
• a digital to analog converter circuit for converting the video signal from the line latch circuit to an analog signal;
• and
• a data output circuit for outputting a signal from the digital to analog converter, wherein a driving frequency of the data driver corresponds to the number of sets of the three video signals.

A data driver for a liquid crystal display comprising:

• a first signal generating circuit for externally producing a source start signal;
• a second signal generating circuit for externally producing a first clock signal;
• a third signal generating circuit for externally producing a load signal;
• a fourth signal generating circuit for externally producing a polarity signal;
• and
• a single integrated circuit including:
• a register circuit for shifting the source start signal corresponding to the first clock signal and outputting a sampling clock signal;
• a data sampling circuit for sampling and outputting a first set of three video signals of odd data and a second set of three video signals of even data, the data sampling circuit receiving all of the video signals simultaneously, each set representing a pixel in the liquid crystal display;
• a 3m.times.n line latch circuit including a first latch unit and a second latch unit for latching the video signals from the data sampling circuit corresponding to the sampling clock signal from the register, the line latch circuit storing and outputting the video signal according to the load signal of the third signal generation circuit, the first latch unit including first and second odd line latches and the second latch unit including first and second even line latches, the first odd line latch receiving the first set of the three video signals and the first even line latch receiving the second set of the three video signals, wherein one horizontal line of display data stored in the first odd and even line latches is stored in the second odd and even line latches in response to the load signal;
• a polarity inversion circuit for inverting a polarity of the video signals from the data sampling circuit;
• and
• a digital to analog converter circuit for converting the video signal from the line latch circuit to an analog signal;
• and
• a data output circuit for outputting a signal from the digital to analog converter, wherein a driving frequency of the data driver corresponds to the number of sets of the three video signals.