PLL frequency synthesizer using plural phase comparators and frequency dividers

A PLL (Phase Locked Loop) frequency synthesizer comprising:

• voltage control oscillation means;
• n-units of phase comparison means, wherein n is a whole number greater than 2, each of said n-units of phase comparison means having respective first and second outputs;
• n-units of oscillation signal frequency-division means corresponding to said n-units of phase comparison means causing the frequency of an oscillation signal from said voltage control oscillation means to be subjected to a first frequency division, wherein an output of each said oscillation signal frequency-division means is a first input of each corresponding phase comparison means;
• n-units of reference signal frequency-division means corresponding to said n-units of phase comparison means causing the frequency of a reference signal to be subjected to a second frequency division, wherein an output of each reference signal frequency-division means is a second input of each corresponding phase comparison means;
• control voltage generating means for generating a control voltage of said voltage control oscillation means in response to respective superpositions of said first and second outputs of said n-units of phase comparison means;
• and
• control means for performing activation-control to sequentially turn on n-units of both of said oscillation signal frequency-division means and said reference signal frequency-division means during each respective cycle interval over n intervals of said reference signal in response to a channel changing instruction.