Output circuit for 3V/5V clock chip duty cycle adjustments
AssigneeCypress Semiconductor Corporation
InventorsPing Xu, John W. Kizziar
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Abstract
The present invention provides an analog biased pre-driver and pad as well as a duty cycle adjustment cell prior to the pre-driver and pad. The pre-driver and pad may operate in either a 3 volt mode, a 5 volt mode or any voltage in between depending only on the power supply voltage present. No production configuration or post-production configuration is required. The present invention utilizes a special bias circuit to reduce the Vcc, temperature and other processing variations. A duty cycle cell produces a range of duty cycles when the circuit is operating between a 3 volt and 5 volt range.
Claims17
A circuit comprising:
- a first circuit configured to generate at least one bias signal in response to a supply voltage;
- and
- a second circuit configured to provide an output timing signal in response to (i) an input timing signal having a duty cycle and (ii) said at least one bias signal, wherein said second circuit comprises a (i) plurality of transistors connected between said supply voltage and ground configured to receive said input timing signal and said at least one bias signal and to generate said output timing signal having a constant duty cycle and (ii) an adjustment transistor coupled to said plurality of transistors and having a gate connected to a junction between a first resistor and a second resistor, said second resistor coupled between said junction and ground, said first resistor coupled between said supply voltage and said junction, wherein said second circuit skews the duty cycle of said input timing signal in response to said at least one bias signal to generate said output timing signal.
A method for producing a constant duty cycle for an input timing signal comprising the steps of:
- (a) generating at least one bias signal in response to a supply voltage;
- and
- (b) skewing a duty cycle of said input timing signal to produce an output timing signal having said constant duty cycle and a reduced sensitivity to variations in said supply voltage, wherein said skewing is generated in response to a (i) plurality of transistors connected between said supply voltage and ground configured to receive said input timing signal and said at least one bias signal and to generate said output timing signal having said constant duty cycle and (ii) an adjustment transistor coupled to said plurality of transistors and having a date connected to a junction between a first resistor and a second resistor, said second resistor coupled between said junction and ground, said first resistor coupled between said supply voltage and said junction, wherein said second circuit skews the duty cycle of said input timing signal in response to said at least one bias signal to generate said output timing signal.
Dependencies are inferred from the claim text.