Driver circuit with precharge and active hold
AssigneeHewlett-Packard Company
InventorBarry J. Arnold
Life of this patent
Estimating the term…
Abstract
A driver circuit for capacitively loaded lines. The driver circuit has both precharge/pull-low and hold-high. The capacitively loaded line is precharged during a precharge phase of a clock signal. The driver circuit is active only during a drive phase of a clock signal. The driver has a hold-up transistor that is sufficiently large to suppress noise coupled into the line during the drive phase, but is substantially smaller than what is required to make pull-up time equal to pull-down time. The driver circuit provides the low noise characteristics of push-pull but with less circuit area and line capacitance than typical push-pull driver circuits.
Claims3
An electronic system comprising:
- a signal line driven by a plurality of driver circuits;
- a precharge transistor that drives the signal line to a first logical level during a clock precharge phase;
- each driver circuit receiving a logical input signal and an enable signal;
- each driver circuit having a first driver transistor that drives the signal line to the first logical level during a clock drive phase when the received logical input signal logically requires the signal line to be at the first logical level and when the received enable signal is in an enable state;
- and
- the first driver transistor being in a high impedance state when the received enable signal is in a disable state, regardless of the state of the received logical input signal.
Dependencies are inferred from the claim text.