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US 5,856,708 AGranted
Polycide/poly diode SRAM load
AssigneeAdvanced Micro Devices, Inc.
InventorDonald L. Wollesen
Life of this patent
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Abstract
A method of manufacturing an SRAM cell with polysilicon diode loads using standard logic technology processing. A P+ polysilicon area and an N+ polysilicon are forms a lateral PN junction. In standard logic technology processing the lateral PN junction is shorted out. In the present invention the lateral PN junction is allowed to function as a polysilicon diode load and an ancilliary lateral PN junction is shorted using a polycide cap layer.
Claims3
A semiconductor integrated circuit element having a single diode load element, comprising:
- an area of p+ polysilicon with an overlying polycide capping layer formed on a surface of the p+ polysilicon;
- an area of n+ polysilicon with an overlying polycide capping layer formed on a surface of the n+ polycide;
- a first end of the n+ polysilicon area and the overlying polycide capping layer connected to a first circuit element;
- a first end of the p+ polysilicon area and the overlying polycide capping layer connected to a gate electrode, wherein the single diode load element is formed in the gate electrode layer;
- and
- a second end of the n+ polysilicon area with a portion of the overlying polycide capping layer removed connected to a second end of the p+ polysilicon area with a portion of the overlying polycide capping layer removed, forming a p/n junction between the p+ polysilicon area and the n+ polysilicon area, wherein there is no polycide capping layer overlying the p/n junction.
3 more elements
Dependencies are inferred from the claim text.