US 5,856,697 A · Integrated dual layer emitter mask and emitter trench for BiCMOS processes

Abstract

A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.

Claims19

Dependent claims

A semiconductor device comprising:

a) a semiconductor substrate having a surface;
b) a protective layer disposed above the semiconductor substrate surface;
c) a trench extending through the protective layer, into the semiconductor substrate, and having a trench bottom that extends below the protective layer and trench sidewalls in contact with said semiconductor substrate;
and
d) a first doped region disposed within the semiconductor substrate, below the trench.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

08/895,270Filed 14 Jul 1997 · continuation

Priority

31 Mar 1993

Granted

5 Jan 1999

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 10/051
Manufacture or treatment: of vertical BJTs
H10D 62/133
Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions: emitter…
H10D 84/0109
Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00,…
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

Integrated dual layer emitter mask and emitter trench for BiCMOS processes

Life of this patent

Integrated dual layer emitter mask and emitter trench for BiCMOS processes

Life of this patent

Abstract

Claims19