Dielectric for amorphous silicon transistors

A thin film transistor structure comprising a plurality of thin film transistors formed on an insulating substrate, some of said transistors being of the floating gate type, and all of said transistors being formed to share a plurality of layers sequentially deposited on the insulating substrate, the thin film transistor structure comprising:

• a metallization layer carried on the substrate and serving as a gate metal for the thin film transistors;
• a dielectric layer deposited on the metallization layer;
• an amorphous silicon layer deposited on the dielectric layer, doped amorphous silicon drain and source regions formed on the amorphous silicon layer and separated by no more than about 5 microns to form a narrow channel between the source and drain;
• the floating gate thin film transistors having a floating gate formed in the dielectric layer;
• and
• the dielectric layer of all the transistors satisfying two structural requirements:
• (1) a high resistivity in the region encapsulating the floating gate in the floating gate transistors, and (2) a nitride layer above the high resistivity layer and in contact with the amorphous silicon layer, the nitride layer being substantially oxide-free to minimize interfacial defect trap density in the channel thereby to increase the switching speed of the thin film transistors;
• and
• wherein the dielectric layer is formed of a single material comprising aluminum nitride which both encapsulates the floating gates and provides a low interfacial defect density at the interface with the amorphous silicon layer;
• and
• wherein the region of the aluminum nitride layer which encapsulates the floating gate is deposited with a random orientation to enhance resistivity, and the region of the aluminum nitride layer which is in contact with the amorphous silicon is deposited with a c-axis vertical orientation with respect to the substrate to enhance dielectric constant.