Method of manufacturing semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorKazuhito Narita
Life of this patent
Estimating the term…
Abstract
The present invention provides a method for reducing the size of a semiconductor chip to be manufactured and improving the precision of processing a fine resist pattern provided for manufacturing the semiconductor chip. In particular, to manufacture a semiconductor chip having a small number of regularly-arranged elements, such as those of a memory cell array, the method uses a fine resist pattern which is formed to have regularly arranged opening portions and a dummy region surrounding the opening portions.
Claims9
A method of manufacturing a semiconductor device, the method comprising the steps of:
- forming a resist layer on a semiconductor substrate having a regular pattern of first grooves, and
- forming a second groove to surround said regular pattern of first grooves.
A method of manufacturing a semiconductor device, comprising:
- coating a surface of a semiconductor substrate with resist;
- and
- opening the resist by use of predetermined pattern which comprises a central pattern and a dummy pattern surrounding the central pattern, the central pattern being configured to form grooves in the resist which are regularly arranged in rows and columns and the dummy pattern being configured to form a surrounding groove in the resist.
Dependencies are inferred from the claim text.