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US 5,856,226 AGranted
Method of making ultra-short channel MOSFET with self-aligned silicided contact and extended S/D junction
AssigneeTexas Instruments - Acer Incorporated
InventorShye-Lin Wu
Life of this patent
Estimating the term…
Abstract
An ultra-short channel MOSFET with the self-aligned silicided contact and the extended ultra-shallow source/drain junction is formed. An extremely short gate region can be defined without being limited with the bottleneck of the existed lithography technology. A good quality gate insulator layer forming from the regrowth of an oxynitride film is provided. A self aligned metal silicide process is performed to form the contacts. A disposable spacer structure is used to remove metal residue and thus the possible path for leakage is eliminated. An ultra shallow region is formed employing the metal silicide as a diffusion source. An extented source/drain region is provided.
Claims22
A method of forming a transistor in a semiconductor substrate, said method comprising the steps of:
- forming a pad insulator layer over said semiconductor substrate;
- forming a stacked layer stacked over said pad insulator layer;
- forming a photoresist layer defined with a gate region pattern over said stacked layer;
- removing a portion of said stacked layer, using said gate region pattern defined on the photoresist layer, for having a hollow space having side walls in said stacked layer subsequently above said pad insulator layer;
- forming a first spacer structure on the side walls of said hollow space over said pad insulator layer for having a narrowed hollow space;
- doping an anti punchthrough region of said semiconductor substrate under said narrowed hollow space with a first concentration of a first dopant, using said first spacer structure and said stacked layer as a first doping mask;
- removing a portion of said pad insulator layer under said narrowed hollow space to said semiconductor substrate and to have an undercut structure under said first spacer structure and said stacked layer;
- forming a regrown pad insulator layer on said semiconductor substrate under said narrowed hollow space and within said undercut structure;
- forming a silicon gate filling to fill within said narrowed hollow space;
- removing said stacked layer and said first spacer structure;
- forming a second spacer structure around a side wall portion of said silicon gate filling;
- removing a portion of said pad insulator layer for leaving a gate insulator layer under said second spacer structure and said silicon gate filling;
- removing said second spacer structure;
- forming a silicon layer over said semiconductor substrate, said silicon layer being conformal with said silicon gate filling and said gate insulator layer;
- forming a third spacer structure on a side wall portion of said silicon layer;
- doping a second concentration of a second dopant to said silicon layer and said third spacer structure;
- forming a metal layer on said silicon layer and said third spacer structure;
- performing a first thermal annealing to said semiconductor substrate to form a metal silicide layer on a top surface of said silicon layer, and to leave an unreacted metal layer on said third spacer structure;
- doping a third concentration of a third dopant to said semiconductor substrate for forming a heavily doped source region and a heavily doped drain region in said semiconductor substrate under a region uncovered by said third spacer structure and said gate insulator layer;
- performing a second thermal annealing to said semiconductor substrate to stabilize said metal silicide layer, and to activate said concentration of third dopant in said heavily doped source region and said heavily doped drain region;
- removing said unreacted metal layer and said third spacer structure;
- removing a portion of said silicon layer located under said third spacer structure, to leave a remaining portion of said silicon layer combining with said silicon gate filling for forming a gate structure;
- doping a fourth concentration of a fourth dopant to said semiconductor substrate, to form an extended shallow junction region containing said fourth dopant, in said semiconductor substrate under a region uncovered by said metal silicide layer and said gate structure;
- forming an insulator layer over said metal silicide layer, said gate insulator layer, and said gate structure;
- performing a third thermal annealing to said semiconductor substrate to activate said fourth dopant in said extended shallow junction region;
- and
- performing a metalization process on said semiconductor substrate to form a set of connections to said gate structure, said heavily doped source region, and said heavily doped drain region.
24 more elements
A method of forming a transistor in a semiconductor substrate, said method comprising the steps of:
- forming a pad insulator layer over said semiconductor substrate;
- forming a stacked layer stacked over said pad insulator layer;
- forming a photoresist layer defined with a gate region pattern over said stacked layer;
- removing a portion of said stacked layer, using said gate region pattern defined on the photoresist layer, for having a hollow space having side walls in said stacked layer subsequently above said pad insulator layer;
- forming a first spacer structure on the side walls of said hollow space over said pad insulator layer for having a narrowed hollow space;
- doping an anti punchthrough region of said semiconductor substrate under said narrowed hollow space with a first concentration of a first dopant, using said first spacer structure and said stacked layer as a first doping mask;
- removing a portion of said pad insulator layer under said narrowed hollow space to said semiconductor substrate and to have an undercut structure under said first spacer structure and said stacked layer;
- forming a regrown pad insulator layer on said semiconductor substrate under said narrowed hollow space and within said undercut structure, said regrown pad insulator layer comprising an oxynitride layer being grown from said semiconductor substrate in a nitrogen and oxygen containing ambient;
- forming a silicon gate filling to fill within said narrowed hollow space;
- removing said stacked layer and said first spacer structure;
- forming a second spacer structure around a side wall portion of said silicon gate filling;
- removing a portion of said pad insulator layer for leaving a gate insulator layer under said second spacer structure and said silicon gate filling;
- removing said second spacer structure;
- forming a silicon layer over said semiconductor substrate, said silicon layer being conformal with said silicon gate filling and said gate insulator layer, said silicon layer comprises a thin layer of undoped amorphous silicon layer formed by a chemical vapor deposition process;
- forming a third spacer structure on a side wall portion of said silicon layer;
- doping a second concentration of a second dopant to said silicon layer and said third spacer structure, said doping being performed with an ion implantation process with nitrogen containing ions;
- forming a metal layer on said silicon layer and said third spacer structure, said metal layer comprising a metal selected from the group consisting of Ti, Co, W, Ni, and Pt;
- performing a first thermal annealing to said semiconductor substrate to form a metal silicide layer on a top surface of said silicon layer, and to leave an unreacted metal layer on said third spacer structure;
- doping a third concentration of a third dopant to said semiconductor substrate for forming a heavily doped source region and a heavily doped drain region in said semiconductor substrate under a region uncovered by said third spacer structure and said gate insulator layer;
- performing a second thermal annealing to said semiconductor substrate to stabilize said metal silicide layer, and to activate said third concentration of third dopant in said heavily doped source region and said heavily doped drain region;
- removing said unreacted metal layer and said third spacer structure;
- removing a portion of said silicon layer located under said third spacer structure, to leave a remaining portion of said silicon layer combining with said silicon gate filling for forming a gate structure;
- doping a fourth concentration of a fourth dopant to said semiconductor substrate, to form an extended shallow junction region containing said fourth concentration of said fourth dopant, in said semiconductor substrate under a region uncovered by said metal silicide layer and said gate structure;
- forming an insulator layer over said metal silicide layer, said gate insulator layer, and said gate structure;
- performing a third thermal annealing to said semiconductor substrate to activate said fourth concentration of fourth dopant in said extended shallow junction region;
- and
- performing a metalization process on said semiconductor substrate to form a set of connections to said gate structure, said heavily doped source region, and said heavily doped drain region.
24 more elements
Dependencies are inferred from the claim text.