Method and apparatus for determining wait states on a per cycle basis in a data processing system

A data processing system, comprising:

• a processor;
• a first plurality of bus terminals, coupled to said processor, said first plurality of bus terminals providing a plurality of address signals external to the data processing system;
• a second plurality of bus terminals, coupled to said processor, said second plurality of bus terminals providing a plurality of data signals external to the data processing system for a write access and receiving the plurality of data signals from external to the data processing system for a read access;
• wait state determining circuitry for receiving a wait state value from external to the data processing system during a bus cycle;
• and
• control circuitry, coupled to said wait state determining circuitry, said control circuitry receiving the wait state value and delaying continuation of the bus cycle for a selected number of wait states, wherein the selected number of wait states is determined by the wait state value,
• wherein the wait state value is received by the data processing system by way of at least one bus terminal of said first and second plurality of bus terminals.

A method for providing wait states in a data processor having a chip select signal, a plurality of address bus terminals and a plurality of data bus terminals, the method comprising the steps of:

• providing a first address value external to the data processor by way of the plurality of address bus terminals during a bus cycle;
• providing a wait state pulse;
• receiving a first wait state value from external to the data processor at a start of the bus cycle;
• in response to receiving the first wait state value, providing by way of the data processor a first number of wait states corresponding to the first wait state value;
• and
• providing a first data value external to the data processor by way of the plurality of data bus terminals for a write access and receiving a first data value from external to the data processor by way of the plurality of data bus terminals for a read access, where the first data value is associated with the first address value.

A method for determining wait states in a data processor having an external bus:

• providing a first address value external to the data processor by way of the external bus during a first bus cycle;
• receiving a first wait state value from external to the data processor during the first bus cycle;
• and
• in response to receiving the first wait state value, providing by way of the data processor a first number of wait states during the first bus cycle;
• providing a second address value external to the data processor by way of the external bus during a second bus cycle;
• receiving a second wait state value from external to the data processor during the second bus cycle;
• and
• in response to receiving the second wait state value, providing by way of the data processor a second number of wait states during the second bus cycle,
• wherein the first number of wait states correspond to the first wait state value, wherein the second number of wait states corresponding to the second wait state value, and wherein the first and second bus cycles are contiguous.

A method for determining wait states in a data processor having an external bus:

• providing a first address value external to the data processor by way of the external bus during a first external bus cycle;
• during the first external bus cycle, receiving a first wait state value from external to the data processor by way of a predetermined portion of the external bus;
• in response to receiving the first wait state value, providing by way of the data processor a first number of wait states on the external bus during the first external bus cycle;
• providing a second address value external to the data processor by way of the external bus during a second external bus cycle;
• during the second external bus cycle, receiving a second wait state value from external to the data processor by way of said predetermined portion of the external bus;
• and
• in response to receiving the second wait state value, providing by way of the data processor a second number of wait states on the external bus during the second external bus cycle,
• wherein said predetermined portion of the external bus is also used to transfer non-wait state information during the first and second external bus cycles.