Speed efficient cache output selector circuitry based on tag compare and data organization

A cache output selector for a multi-way set-associative cache memory, said cache memory for storing a plurality of lines of data, each line data containing a plurality of words of data, and for providing for simultaneous access of words grouped as a multiple-word, said cache memory comprising a plurality of data arrays wherein consecutive multiple-words of each line of data in the plurality of lines of data reside in different data arrays in the plurality of data arrays, said cache memory comprising a switchably selectable output path for outputting an addressed multiple-word either via a pre-fetch buffer path from a set of pre-fetch latches or via a bypass path which bypasses said set of pre-fetch latches said cache output selector comprising:

• for each data array of the plurality of data arrays, a tag matching circuit for checking whether an addressed multiple-word resides in the data array and for producing a tag match signal to indicate whether the addressed multiple-word resides in the data array;
• a qualifying tag match circuit which receives the respective tag match signals from each of the tag matching circuits and produces respective qualified tag match signals for each of the tag matching signals;
• for each data array of the plurality of data arrays, a qualifying multiplexor which receives the respective qualified tag match signals from the qualifying tag matching circuit as data inputs, a set selector signal which selects one of said data inputs for output, and at least one qualifying signal used to qualify when said qualifying multiplexor outputs said selected data input as a qualified data array output enable signal;
• and
• a qualifying output path select circuit which receives said respective tag match signals from each of said tag matching circuits as data input, said at least one qualifying signal as a qualifying input, and an output path select signal as a select input, said qualifying output path select circuit selecting one of said prefetch path or said bypass path from which to output said addressed multiple-word and qualifying an output enable signal.