Method of generating code for programmable processors, code generator and application thereof

A method of simulating the execution of code on a programmable processor, being implemented in hardware and having an instruction set, said method comprising the steps of:

• representing said processor as a directed bipartite graph with first and second sets of vertices and with edges, said graph comprising essentially all information about the instruction set and the hardware of said processor,
• said first set of vertices representing storage elements in said processor,
• said second set of vertices representing micro-operations in said processor;
• said edges representing valid connections between micro-operations and said storage elements, and
• said connections modeling the data flow in said processor,
• linking said graph to tools and libraries requited for said simulation, and
• executing said simulation whereby the required information about said processor is extracted from said graph.

A retargetable simulator that performs the simulation of the execution of code on a programmable processor being embedded in an electronic system comprising:

• an electronic system with an embedded programmable processor,
• first tools to build a directed bipartite graph which internally represents said programmable processor with first and second sets of vertices and with edges, said graph comprising essentially all information about the instruction set and the hardware of said processor, said first set of vertices representing storage elements in said processor, and said second set of vertices representing operations in said processor;
• second tools and libraries required for simulating said processor, and
• means to link said graph to said second tools and libraries whereby the information about said processor required during simulation is extracted from said graph.

A method of synthesizing a programmable processor being implemented in hardware, comprising the steps of:

• representing said processor as a directed bipartite graph with first and second sets of vertices and with edges, said graph comprising essentially all information about the instruction set and the hardware of said processor,
• said first set of vertices representing storage elements in said processor;
• said second set of vertices representing micro-operations in said processor;
• said edges representing valid connections between said micro-operations and said storage elements, said connections modeling the data flow in said processor;
• linking said graph to tools and libraries required for generating a netlist of hardware building blocks;
• implementing said processor as a hardware device according to said netlist.