Method and apparatus for identifying flip-flops in HDL descriptions of circuits without specific templates

A method for detecting clock edge-sensitive behavior from a functional description of a circuit and inferring a hardware implementation of the detected clock edge-sensitive behavior, the functional description comprising one or more processes, execution of each of the one or more processes affecting one or more nets, each of the one or more nets represented by a directed acyclic graph (DAG), said method comprising the steps of:

• for each of the one or more nets affected by each of the one or more processes;
• using the DAG representing a current one of the one or more nets affected by a current one of the one or more processes, determining whether the behavior of the current net is clock edge-sensitive;
• and
• when the behavior of the current net is determined to be clock edge-sensitive by said determining step:
• extracting an asynchronous control expression from the DAG representing the current net;
• extracting a data input expression from the DAG representing the current net;
• and
• implementing the current net as a flip-flop using the extracted asynchronous control expression and the extracted data input expression,
• wherein said step of extracting an asynchronous control expression further comprises the step of:
• rebuilding the DAG representing the current net with all event operators set equal to false.

A method for detecting clock edge-sensitive behavior from a functional description of a circuit and inferring a hardware implementation of the detected clock edge-sensitive behavior, the functional description comprising one or more processes, execution of each of the one or more processes affecting one or more nets, each of the one or more nets represented by a directed acyclic graph (DAG), said method comprising the steps of:

• for each of the one or more nets affected by each of the one or more processes:
• using the DAG representing a current one of the one or more nets affected by a current one of the one or more processes, determining whether the behavior of the current net is clock edge-sensitive;
• and
• when the behavior of the current net is determined to be clock edge-sensitive by said determining step;
• extracting an asynchronous control expression from the DAG representing the current net;
• extracting a data input expression from the DAG representing the current net;
• and
• implementing the current net as a flip-flop using the extracted asynchronous control expression and the extracted data input expression,
• wherein said step of extracting a data input expression further comprises the step of:
• rebuilding the DAG representing the current net to remove operators that select a value for the current net based on asynchronous control.