Flexible resource access in a microprocessor

A method of accessing special registers comprising:

• defining a first register level and a second register level, wherein said first register level includes a plurality of primary registers and a pointer to said second register level, and said second register level includes a plurality of special registers;
• decoding a first operand field of an instruction, wherein said first operand field identifies one of said plurality of primary registers or said pointer to said second register level;
• decoding a second operand field of an instruction if said first operand field identifies said pointer to said second register level;
• and
• accessing one of said plurality of special registers of said second register level identified by said second operand field.

A microprocessor with flexible resource allocation comprising:

• a plurality of special registers including one or more remote special registers and one or more local special registers;
• a remote special register bus coupled to said one or more remote special registers, wherein said remote special registers are configured to be accessed via said remote special register bus;
• a special register unit coupled to said remote special register bus;
• a decode unit coupled to said special register unit, wherein said decode unit is configured to route instruction information to said special register unit, said special register unit is configured to decode said instruction information and configured to access a special register identified by said instruction information;
• whereby said decode unit is configured to handle an access to a special register in substantially the same way as an access to a primary register.