Pattern generation apparatus and method for SDRAM
AssigneeAdvantest Corporation
InventorsOsamu Yamada, Koji Hara
Life of this patent
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Abstract
A test pattern generation apparatus and method for an SDRAM can easily generate a test pattern for the SDRAM by having a specific wrap conversion circuit or an address conversion method. The wrap conversion circuit is provided to receive two kinds of data from a pattern generator and converts the data through a predetermined logic circuit information. The test pattern generation method for the SDRAM is carried out by inputting the column address data Y0-Y2 and the wrap address data Z0-Z2, and by generating output data which has been converted by a predetermined logic equation. The test pattern generation apparatus and method can also include an address inversion scramble for the converted output.
Claims7
A test pattern generation apparatus for generating a test pattern to test a synchronous dynamic random access memory (SDRAM) characterized in that:
- a wrap conversion means (40) is provided which receives two kinds of data (Y0-Yn and Z0-Zn) from a pattern generator (10) and converts the data based on predetermined logic circuit information.
A test pattern generation method for generating a test pattern to test a synchronous dynamic RAM (SDRAM) characterized in that:
- inputting column address data (Y0-Y2) from a pattern generator to a wrap address conversion circuit;
- inputting wrap address data (Z0-Z2) from the pattern generator to the wrap address conversion circuit;
- outputting a converted address (Y0-Y2) from the wrap address conversion circuit based on the following logic equations;
- Y0=Y0. XOR. Z0
- Y1=Y1. XOR. Z1
- Y2=Y2. XOR. Z2.
A test pattern generation method for generating a test pattern to test a synchronous dynamic RAM (SDRAM) characterized in that:
- inputting column address data (Y0-Y2) from a pattern generator to a wrap address conversion circuit;
- inputting wrap address data (Z0-Z2) from the pattern generator to the wrap address conversion circuit;
- outputting a converted address (Y0-Y2) from the wrap address conversion circuit based on the following logic equations;
- Y0=Y0. XOR. Z0
- Y1=(Y0. AND. Z0). XOR. (Y1. XOR. Z1)
- Y2=(((Y0. AND. Z0). AND. (Y1. XOR. Z1)). OR. (Y1. AND. Z1)). XOR. (Y2. XOR. Z2).
Dependencies are inferred from the claim text.