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US 5,854,772 AGranted
Decoder circuit with less transistor elements
AssigneeNEC Corporation
InventorTakayuki Suzu
Life of this patent
Estimating the term…
Abstract
Eight decoder circuits each of which comprising two transfer-gate-circuit transistors and two transistors for fixation of unselected level are connected in series and arranged in three hierarchies. Consequently, the decoder circuit is capable of selecting one output signal wire out of eight output signal wires by three address input signals so as to output an output of a high level to the selected output signal wire.
Claims12
A decoder circuit for decoding signals comprising:
- an input signal wire for transmitting an input signal;
- a first output signal wire for transmitting a first output signal;
- a second output signal wire for transmitting a second output signal;
- a first address signal wire for transmitting a first TRUE address input signal;
- a second address signal wire for transmitting a second BAR address input signal which is the antiphase of the first TRUE address signal;
- a first n-MOS transistor having its source terminal connected to the input signal wire, its gate terminal connected to the first address signal wire and its drain terminal connected to the first output signal wire;
- a second n-MOS transistor having its source terminal connected to a power source on the ground level, its gate terminal connected to the second address signal wire and its drain terminal connected to the first output signal wire;
- a third n-MOS transistor having its source terminal connected to the input signal wire, its gate terminal connected to the second address signal wire and its drain terminal connected to the second output signal wire;
- and
- a fourth n-MOS transistor having its source terminal connected to a power source on the ground level, its gate terminal connected to the first address signal wire and its drain terminal connected to the second output signal wire.
7 more elements
A decoder circuit for decoding signals comprising:
- an input signal wire for transmitting an input signal;
- a first output signal wire for transmitting a first output signal;
- a second output signal wire for transmitting a second output signal;
- a first address signal wire for transmitting a first TRUE address input signal;
- a second address signal wire for transmitting a second BAR address input signal which is the antiphase of the first TRUE address signal;
- a first n-MOS transistor having its source terminal connected to the input signal wire, its gate terminal connected to the first address signal wire and its drain terminal connected to the first output signal wire;
- a first p-MOS transistor having its source terminal connected to a power source, its gate terminal connected to the first address signal wire and its drain terminal connected to the first output signal wire;
- a third n-MOS transistor having its source terminal connected to the input signal wire, its gate terminal connected to the second address signal wire and its drain terminal connected to the second output signal wire;
- and
- a second p-MOS transistor having its source terminal connected to a power source, its gate terminal connected to the second address signal wire and its drain terminal connected to the second output signal wire.
7 more elements
A decoder circuit for decoding signals comprising:
- an input signal wire for transmitting an input signal;
- a first output signal wire for transmitting a first output signal;
- a second output signal wire for transmitting a second output signal;
- a first address signal wire for transmitting a first TRUE address input signal;
- a second address signal wire for transmitting a second BAR address input signal which is the antiphase of the first TRUE address signal;
- a third p-MOS transistor having its source terminal connected to the input signal wire, its gate terminal connected to the first address signal wire and its drain terminal connected to the first output signal wire;
- a second n-MOS transistor having its source terminal connected to a power source on the ground level, its gate terminal connected to the first address signal wire and its drain terminal connected to the first output signal wire;
- a fourth p-MOS transistor having its source terminal connected to the input signal wire, its gate terminal connected to the second address signal wire and its drain terminal connected to the second output signal wire;
- and
- a fourth n-MOS transistor having its source terminal connected to a power source on the ground level, its gate terminal connected to the second address signal wire and its drain terminal connected to the second output signal wire.
7 more elements
A decoder circuit for decoding signals comprising:
- an input signal wire for transmitting an input signal;
- a first output signal wire for transmitting a first output signal;
- a second output signal wire for transmitting a second output signal;
- a first address signal wire for transmitting a first TRUE address input signal;
- a second address signal wire for transmitting a second BAR address input signal which is the antiphase of the first TRUE address signal;
- a third p-MOS transistor having its source terminal connected to the input signal wire, its gate terminal connected to the first address signal wire and its drain terminal connected to the first output signal wire;
- a fourth p-MOS transistor having its source terminal connected to the input signal wire, its gate terminal connected to the second address signal wire and its drain terminal connected to the second output signal wire;
- a fifth p-MOS transistor having its source terminal connected to a power source, its gate terminal connected to the second address signal wire and its drain terminal connected to the first output signal wire;
- and
- a sixth p-MOS transistor having its source terminal connected to a power source, its gate terminal connected to the first address signal wire and its drain terminal connected to the second output signal wire.
7 more elements
Dependencies are inferred from the claim text.