Address input buffer with signal converter

An address input buffer for a semiconductor memory device which is capable of converting address signals from external pins to access memory cells uniformly comprises of:

• address buffering means buffering at least two external address signals;
• multiplexing means receiving the external address signals buffered by said address buffering means and outputting the external address signals as the corresponding internal address signals through the output terminals thereof;
• and
• multiplexing control means selectively transferring the external address signals buffered by said address buffering means to said output terminals,
• wherein significant bits sequence order of the internal address signals outputted from the output terminals of the multiplexing means is proportional to significant bits sequence order of the external address signals or reciprocal to significant bits sequence order of the external address signals in accordance with an output signal state of the multiplexing control means, and
• wherein said multiplexing means produces the internal address signals corresponding respectively to the external address signals in the first case and those in the second case by inverting the external address signals.

An address input buffer for a semiconductor memory device comprising:

• address buffering means for buffering at least two external address signals A1 and A2;
• at least two output terminals for outputting the external address signals A1 and A2 buffered by said address buffering means as internal address signals AI.sub.-- 1 and AI.sub.-- 2, respectively;
• multiplexing means electrically connected between said address buffering means and said output terminals, for selectively transferring the external address signals A1 and A2 buffered by said address buffering means to said output terminals;
• and
• multiplexing control means for controlling said multiplexing means wherein said multiplexing control means includes means for storing a status before a power signal is turned on, to produce an internal address signal in response to a true address for an operation before the power signal is turned on and in response to a complementary address for the subsequent operation.