DRAM having a power supply voltage lowering circuit

Abstract

A DRAM includes first to third voltage lowering circuits for lowering a power supply voltage supplied from the exterior and supplying the lowered voltage to an internal circuit. The first to third voltage lowering circuits are separately provided. The first voltage lowering circuit is a feedback type circuit having a P-channel MOS transistor. The first voltage lowering circuit is an exclusive circuit for creating a first potential by lowering the power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to a RAS signal input buffer, CAS signal input buffer and WE signal input buffer. The second voltage lowering circuit is a feedback type circuit having a P-channel MOS transistor or source follower type circuit having an N-channel MOS transistor. The second voltage lowering circuit is an exclusive circuit for creating a second potential by lowering the power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to a V.sub.BL generating circuit for generating a bit line precharge potential and a V.sub.PL generating circuit for generating a cell plate potential. The third voltage lowering circuit is a source follower type circuit having an N-channel MOS transistor.

Dependencies are inferred from the claim text.