Semiconductor memory device having a plurality of blocks each including a parallel/serial conversion circuit

A semiconductor memory device comprising a plurality of blocks, a plurality of first selection signals and a plurality of second selection signals being provided to the plurality of blocks,

• wherein each of the plurality of blocks includes:
• a memory cell array;
• a read/write circuit for simultaneously writing a plurality of data into the memory cell array when a corresponding one of the plurality of first selection signals is active;
• a serial/parallel conversion circuit for receiving the plurality of data, the data being sequential, and for outputting the plurality of sequential data to the read/write circuit in a parallel manner along the time axis;
• a gate controlled by a corresponding one of the plurality of second selection signals, the gate outputting the plurality of sequential data to the serial/parallel conversion circuit when the corresponding one of the plurality of second selection signals is active, and
• wherein only one of the plurality of second selection signals is allowed to be active at a given time, while the other second selection signals remain non-active.

A semiconductor memory device comprising a plurality of blocks, a plurality of first selection signals, a plurality of second selection signals, and a plurality of third selection signals being provided to the plurality of blocks,

• wherein each of the plurality of blocks includes:
• a memory cell array;
• a read/write circuit for simultaneously reading out a plurality of data from the memory cell array and subsequently simultaneously writing a plurality of further data into the memory cell array when a corresponding one of the plurality of first selection signals is active;
• a parallel/serial conversion circuit for outputting the plurality of simultaneously read out data, the outputting being performed data by data in a serial manner along the time axis;
• a transfer gate for a reading operation controlled by a corresponding one of the plurality of second selection signals, the gate outputting the plurality of data from the parallel/serial conversion circuit when the corresponding one of the plurality of second selection signals is active;
• a serial/parallel conversion circuit for receiving the plurality of further data, the further data being sequential, and for outputting the plurality of sequential data to the read/write circuit in a parallel manner along the time axis;
• and
• a transfer gate for a writing operation controlled by a corresponding one of the plurality of third selection signals, the gate outputting the plurality of sequential data to the serial/parallel conversion circuit when the corresponding one of the plurality of third selection signals is active, and
• wherein only one of the plurality of second selection signals is allowed to be active at a given time, while the other second selection signals remain non-active, and only one of the plurality of third selection signals is allowed to be active at a given time, while the other third selection signals remain non-active.