Non-volatile semiconductor memory device with diagnostic potential generator for individually checking whether memory cells are over-erased
AssigneeNEC Corporation
InventorMitsuru Sekiguchi
Life of this patent
Estimating the term…
Abstract
When floating gate type memory transistors undesirably enter into an over-erased state, a diagnostic potential generator supplies a first diagnostic potential to a source line and second and third diagnostic potentials to non-selected word lines and a selected word line; the potential difference between the first diagnostic potential and the second diagnostic potential causes an over-erased memory transistor to be turned off, and the potential difference between the first diagnostic potential and the third diagnostic potential allows an over-erased memory transistor to turn on so as to identify each over-erased memory transistor by its row and column addresses.
Claims9
An electrically erasable and programmable read only memory device comprising:
- a memory cell array including a plurality of memory transistors, each of said plurality of memory transistors having a variable threshold and storing a data bit having one of first and second logic levels corresponding to first and second thresholds, respectively;
- a plurality of bit lines selectively connected to current input nodes of said plurality of memory transistors;
- a plurality of word lines selectively connected to control nodes of said plurality of memory transistors for applying potentials to word lines of memory transistors of the memory cell array;
- a current discharging path connected to discharging nodes of said plurality of memory transistors;
- a data logic level discriminating means selectively connected to said plurality of bit lines, for determining whether a memory transistor associated with a selected bit line has said first threshold or said second threshold on the basis of an amount of current passing through the selected bit line;
- and
- an over-erased state discriminating means for supplying a first diagnostic potential to said discharging path, and for sequentially changing said plurality of word lines from a second diagnostic potential to a third diagnostic potential such that said data logic level discriminating means determines whether a memory transistor associated with a selected bit line and receiving said third diagnostic potential has entered into an over-erased state represented by a third threshold that is outside of a potential range between said first threshold and said second threshold, a potential difference between said first diagnostic potential level and said second diagnostic potential level causing a memory transistor in said over-erased state to be turned off, a potential difference between said first diagnostic potential level and said third diagnostic potential level allowing a memory transistor in said over-erased state to turn on.
A method for determining whether a memory cell of a memory cell array is in an over-erased state, comprising:
- applying a first diagnostic potential level to a discharging path associated with a memory cell;
- applying a second diagnostic potential to a word line of the memory cell to cause the memory cell to be turned off if the memory cell is in an over-erased state;
- changing the potential applied to the word line of the memory cell from the second diagnostic potential to a third diagnostic potential to cause the memory cell to be turned on if the memory cell is in an over-erased state;
- and
- detecting a change in a logic level of a bit line of the memory cell corresponding to the change from the second diagnostic potential to the third diagnostic potential.
Dependencies are inferred from the claim text.