Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell portion;
• and
• at least one output part being provided with a plurality of read data which are read from said memory cell portion and a mode selection signal, said output part including
• a logic decision circuit for producing a control signal indicating whether logic levels of said plurality of read data are all the same, and
• an output circuit which includes a transmission path having transistors and having logic gates all of which have only a single input terminal, and said output circuit controls to operate in at least one of two states, a first state being to transmit first read data to an output port of said output circuit through said transmission path and a second state being to set said output port to be at a high-impedance state depending on said control signal and said mode selection signal;
• wherein when the mode selection signal indicates a normal mode, said output circuit operates in said first state, and when the mode selection signal indicates a test mode, said output circuit operates to be in one of said first state and said second state depending on said control signal.