Two-dimensional PE array, content addressable memory, data transfer method and mathematical morphology processing method

A CAM (content addressable memory) comprising:

• means for writing and reading data to and from words by using an address;
• shift mode means for shifting contents of a hit-flag register;
• and
• means for simultaneously carrying out said shifting of the contents of said hit-flag register and the writing and reading of the data to and from said words by using an address.

A data transfer method in a two-dimensional PE array comprising the steps of:

• forming a one-dimensional array of w words, where w is any natural number;
• transferring data between q.times.r CAMs (content addressable memories), where q and r are any integers equal to or greater than two, by external input and output of contents of a hit-flag register through an upper shift I/O port and a lower shift I/O port, said hit-flag register having shift up and shift down functions;
• connecting with hit-flag shift lines the lower shift I/O port of one CAM of two horizontally adjacent CAMs of said CAMs to the upper shift I/O port of the other CAM of said two horizontally adjacent CAMs;
• arranging w words in each of said CAMs in m rows by n columns in a zigzag fashion, where m and n are any natural number satisfying w=m.times.n;
• and
• mapping each of said w words in said CAMs to at least one of said PEs.

A data transfer method between CAMs (content addressable memories) comprising the steps of:

• forming a one-dimensional array of w words, where w is any natural number;
• transferring data between q.times.r CAMs, where q and r are any integers equal to or greater than two, by external input and output of contents of a hit-flag register through an upper shift I/O port and a lower shift I/O port, said hit-flag register having shift up and shift down functions;
• and
• performing data transfer simultaneously from odd row CAMs to even row CAMs, and from said even row CAMs to said odd row CAMs of said CAMs arranged in q rows, said data transfer being carried out simultaneously for entire CAMs in each of said rows of said CAMs.

A data transfer method in CAM (content addressable memory) comprising the steps of:

• forming a one-dimensional array of w words, where w is any natural number;
• executing maskable search comparing date stored in said word with search data and ignoring the comparison of part of the search data;
• transferring a content of a particular bit of a first word specified by said maskable search to a first hit-flag register having shift up and shift down functions;
• shifting up or shifting down the first hit-flag register having the trasferred content and transferring the shifted content to a second hit-flag register of a second word;
• and
• transferring the content of the second hit-flag register to a particular bit of the second word, by using a partial and parallel write writing the search data into a bit of the second word corresponding to an unmasked bit of the search data, wherein the second hit-flag register of the second word has a particular value.

A CAM (content addressable memory) data transfer method comprising the steps of:

• writing and reading data to and from words by using an address;
• carrying out a shift mode of a hit-flag register;
• and
• performing simultaneously the shift mode of said hit-flag register and the writing and reading of said data to and from said words by using an address.

A two-dimensional PE array comprising:

• q.times.r CAMs (content addressable memories), where q and r are any integers equal to or greater than two, each of said CAMs including one dimensionally arrayed w words each of which has an original image field, a next image field and a shift image field, where w is any natural number, a hit-flag register having shift up and shift down functions, and an upper shift I/O port and a down shift I/O port for inputting from or outputting to outside contents of said hit-flag register;
• hit-flag connection lines for connecting the lower shift I/O port of one CAM of two horizontally adjacent CAMs of said CAMs to the upper shift I/O port of the other CAM of said two horizontally adjacent CAMs;
• wherein each of said w words in each of said CAMs is mapped successively to at least one of PEs which are arranged in m rows by n columns and are connected in a zigzag, where w, m and n are any natural numbers satisfying w=m.times.n, thereby forming a CAM array comprising m.times.q PEs in vertical direction and n.times.r PEs in a horizontal direction;
• and
• a controller for providing said CAM array with a single control instruction stream.