US 5,854,757 AGranted

Super-compact hardware architecture for IDCT computation

AssigneeLSI Logic Corporation

InventorGregg Dierke

Life of this patent

Estimating the term…

Loading patent…

Abstract

An Inverse Discrete Cosine Transform processor employs symmetry and reusable elements to use a fewer number of gates while maintaining processing speed at an acceptable level. Even and odd sums are generated simultaneously by even and odd sum generators. A butterfly operation is then performed on the on the even and odd sums to produce pairs of transformed elements simultaneously. For an 8.times.8 block, the even and odd sum generators can be designed to a generate four pairs of even and odd sums sequentially. This design allows a single row or column of eight elements to be processed in 4 clock cycles. A horizontal transformation on all eight rows of the block can be performed in 32 cycles. A vertical transformation can then be performed by storing the transformed rows in a second memory, reading out columns from the second memory, and using the same hardware to generate the sums and perform the butterfly operation on the columns. An entire two-dimensional transformation can be performed in only 64 clock cycles.

Claims16

Dependent claims

A processor for performing a cosine transform on blocks of data, the processor comprising:

a first multiplier for scaling the blocks of data into blocks of scaled data;
a first memory for storing the blocks of scaled data and reading out the scaled data in a first direction, the scaled data being read out in vectors having 2n elements, where n is a positive integer;
an even sum generator that generates even sums from even elements of the vectors read out of the first memory;
and odd sum generator that generates odd sums from odd elements of the vectors read out of the first memory;
a first adder that adds together the even and odd sums;
and
a subtracter that subtracts the odd sums from the even sums, the operations of the first adder and subtracter being performed simultaneously;
wherein the even sum generator includes a first control for generating terms from the even elements of the vectors read out of the first memory, and a second adder for summing the terms generated by the first control;
wherein the odd sum generator includes a second control for generating terms from the odd elements of the vectors read out of the first memory, a third adder for summing the terms generated by the second control, and means for selectively multiplying the odd sums generated by the third adder with a constant value, whereby the first and second data controls generate terms for n different pairs of odd and even sums;
and
wherein the means for selectively multiplying includes a second multiplier for multiplying an output of the odd sum generator with the constant value;
and a multiplexer having a first input coupled to an output of the odd sum generator and a second input coupled to an output of the multiplier, the first input being selected when it is not desired to multiply the odd sum by the constant value, the second input being selected when it is desired to multiply the odd sum by the constant value.

9 more elements

A processor for performing a cosine transform on blocks of data, the processor comprising:

a first memory for storing the blocks of data and reading out the data in a first direction, the data being read out in vectors having 2n elements, where n is a positive integer;
an even sum generator that generates even sums from even elements of the vectors read out of the first memory;
an odd sum generator that generates odd sums from odd elements of the vectors read out of the first memory;
a first adder that adds together the even and odd sums;
and
a subtracter that subtracts the odd sums from the even sums, the operations of the first adder and subtracter being performed simultaneously;
wherein the even sum generator includes a first control for generating terms from the even elements of the vectors read out of the first memory, and a second adder for summing the terms generated by the first control;
wherein the odd sum generator includes a second control for generating terms from the odd elements of the vectors read out of the first memory, and a third adder for summing the terms generated by the second control, whereby the first and second data controls generate terms for n different pairs of odd and even sums;
wherein the odd sum generator further includes a means for selectively multiplying the odd sums generated by the third adder with a constant value;
wherein the means for selectively multiplying includes:
a multiplier for multiplying an output of the odd sum generator with the constant value;
and
a multiplexer having a first input coupled to an output of the odd sum generator and a second input coupled to an output of the multiplier, the first input being selected when it is not desired to multiply the odd sum by the constant value, the second input being selected when it is desired to multiply the odd sum by the constant value.

10 more elements

Dependencies are inferred from the claim text.