US 5,854,755 A · Clock frequency multiplication device

Abstract

A clock frequency multiplication device comprising a first multiplier for generating an oscillating frequency every first half of a period of an input clock signal where the input clock signal is high in logic, counting the oscillating frequency, dividing the resultant count data at a division ratio of 1/2.sup.n, where n is a natural number, providing the divided count data as a preset signal and down counting the count data in response to the preset signal to multiply the frequency of the input clock signal by a desired number for the first half of the period of the input clock signal, a second multiplier for multiplying the frequency of the input clock signal by the desired number for the latter half of the period of the input clock signal where the input clock signal is low in logic, in the same manner as that of the first multiplier, a control unit for controlling the first and second multipliers in such a manner that they can be operated for the opposite halves of the period of the input clock signal and setting the division ratio of the first and second multipliers to control a multiplication ratio thereof, and an output stage for mixing output signals from the first and second multipliers and outputting the mixed result as a multiplied frequency clock signal.

Claims16

Dependent claims

A clock frequency multiplication device comprising:

first multiplication means for generating an oscillating frequency every half of a period of an input clock signal when the input clock signal is high in logic, by counting the oscillating frequency, dividing resultant count data by 2.sup.n, where n is a natural number, to provide divided count data as a preset signal which is down counted to multiply the frequency of the input clock signal by a desired number for said first half of the period of the input clock signal;
second multiplication means for multiplying the frequency of the input clock signal by said desired number for the latter half of the period of the input clock signal when the input clock signal is low in logic, by counting the oscillating frequency dividing the resultant count data by 2.sup.n, where n is a natural number to provide divided count data as a preset signal down counted to multiply the frequency of the input clock signal by said desired number which is for the latter half of the period of the input clock signal;
control means for controlling said first and second multiplication means in such a manner that they can be operated for the opposite halves of the period of the input clock signal and setting a division ratio of said first and second multiplication means ;
and
output means for mixing output signals from said first and second multiplication means and outputting the mixed result as a multiplied frequency clock signal.

2 more elements

A clock frequency multiplication device comprising:

first multiplication means for generating an oscillation frequency every half of a period of an input clock signal when the input clock signal is high in logic, counting the oscillating frequency to produce a counted number, dividing the counted number by a desired number of 2.sup.n to produce a divided number, where n is a natural number, latching and providing the divided number as a preset number to a down counter, down counting the preset number by said oscillation frequency until a borrow signal is generated, reloading the divided number again as the preset number of down counter and repeating down counting until said desired number of borrow signals are generated, and thus said desired number of borrow signal pulses can be obtained during a first half of input clock signal period,
second multiplication means for generating said oscillation frequency every half of a period of an input clock signal when the input clock signal is low in logic, counting the oscillating frequency to produce a counted number, dividing the counted number by a desired number of 2.sup.n to produce a divided number, where n is a natural number, latching and providing the divided number as a preset number to a down counter, down counting the preset number by said oscillation frequency until a borrow signal is generated, reloading the divided number again as the preset number of down counter and repeating down counting until said desired number of borrow signals arc generated, and thus said desired number of borrow signal pulses can be obtained during a first half of input clock signal period, control means for controlling said first and second multiplication means in such a manner that they operate oppositely to each other, thus for the opposite halves of periods of the input clock signal respectively and setting said desired number of said first and second multiplication means to control a multiplication ratio thereof;
and
output means for mixing borrow signals from said first and second multiplication means and generating mixed result as a multiplied frequency signal.

1 more element

A clock frequency multiplication method comprising:

(a) generating an oscillating frequency every half of a period of an input clock signal when the input clock signal is high in logic, by counting the oscillating frequency, dividing resultant count data by 2.sup.n, where n is a natural number, to provide divided count data as a preset signal which is down counted to multiply the frequency of the input clock signal by a desired number for said first half of the period of the input clock signal;
(b) multiplying the frequency of the input clock signal by said desired number for the latter half of the period of the input clock signal when the input clock signal is low in logic, by counting the oscillating frequency dividing the resultant count data by 2.sup.n, where n is a natural number to provide divided count data as a preset signal down counted to multiply the frequency of the input clock signal by said desired number which is for the latter half of the period of the input clock signal;
(c) for controlling said steps (a) and (b) in such a manner that they can be operated for the opposite halves of the period of the input clock signal and setting a division ratio of said steps (a) and (b);
and
(d) mixing output signals from said steps (a) and (b) and outputting the mixed result as a multiplied frequency clock signal.

2 more elements

A clock frequency multiplication method comprising:

(a) generating an oscillation frequency every half of a period of an input clock signal when the input clock signal is high in logic, counting the oscillating frequency to produce a counted number, dividing the counted number by a desired number of 2.sup.n to produce a divided number, where n is a natural number, latching and providing the divided number as a preset number to a down counter, down counting the preset number by said oscillation frequency until a borrow signal is generated, reloading the divided number again as the preset number of down counter and repeating down counting until said desired number of borrow signals are generated, and thus said desired number of borrow signal pulses can be obtained during a first half of input clock signal period,
(b) generating said oscillation frequency every half of a period of an input clock signal when the input clock signal is low in logic, counting the oscillating frequency to produce a counted number, dividing the counted number by a desired number of 2.sup.n to produce a divided number, where n is a natural number, latching and providing the divided number as a preset number to a down counter, down counting the preset number by said oscillation frequency until a borrow signal is generated, reloading the divided number again as the preset number of down counter and repeating down counting until said desired number of borrow signals are generated, and thus said desired number of borrow signal pulses can be obtained during a first half of input clock signal period,
(c) controlling said steps (a) and (b) in such a manner that they operate oppositely to each other, thus for the opposite halves of periods of the input clock signal respectively and setting said desired number to control a multiplication ratio thereof;
and
(d) mixing borrow signals from said steps (a) and (b) and generating mixed result as a multiplied frequency signal.

2 more elements

Dependencies are inferred from the claim text.

Clock frequency multiplication device

Life of this patent

Clock frequency multiplication device

Life of this patent

Abstract

Claims16