Circuit partitioning technique for use with multiplexed inter-connections

A method for emulating a logic circuit in a plurality of programmable logic devices, comprising the steps of:

• partitioning a representation of said logic circuit into a plurality of logic blocks, in accordance with a single cost constraint, said cost constraint including functions of the number of logic gates and the number of pins of each logic, each logic block having a plurality of logic gates and a plurality of pins for connecting said logic block with other logic blocks in said plurality of logic blocks;
• and
• assigning each of said logic blocks to be implemented on one of said programmable logic device;
• wherein said cost constraint is given by:
• .function.(G.sub.i,cP.sub.i).ltoreq.G.sub.max
• where .function. is a function of the quantities G.sub.i and cP.sub.i, G.sub.i being the number of logic gates in said logic block G.sub.max being said predetermined number of logic gates, c being a weighting factor expressing a cost of a pin in terms of a logic gate, and P.sub.i being the number of pins in said logic block.