Semiconductor IC with a plurality of processing circuits which receive parallel data via a parallel data transfer circuit

A semiconductor integrated circuit comprising:

• a memory cell array including a plurality of data line groups, a plurality of word lines intersecting said plurality of data line groups, and a plurality of memory cells disposed at desired intersections between said plurality of data line groups and said plurality of word lines;
• a parallel data transfer circuit for transferring a plurality of data groups in parallel from said plurality of data line groups;
• and
• a plurality of processing circuits for receiving said plurality of data groups transferred from said parallel data transfer circuit, as their input signals,
• wherein said parallel data transfer circuit is enabled to transfer two or more of said plurality of data groups to each of said plurality of processing circuits by sequentially selecting two or more of said plurality of data line groups and coupling to each of said plurality of processing circuits and wherein the adjoining ones of said plurality of processing circuits can input the same data group from the same data line groups.

A semiconductor integrated circuit comprising:

• first and second memory cell arrays each of which including a plurality of data lines, a plurality of word lines intersecting said plurality of data lines, and a plurality of memory cells disposed at desired intersections between said plurality of data lines and said plurality of word lines;
• a first parallel data transfer circuit coupled to first group, second group, and third group data lines of said plurality of data lines of said first memory cell array;
• a second parallel data transfer circuit coupled to first group, second group, and third group data lines of said plurality of data lines of said second memory cell array;
• and
• first, second, and third processing circuits coupled to said first and second parallel data transfer circuits,
• wherein said first parallel data transfer circuit selects one of said first group, second group, and third group data lines of said plurality of data lines of said first memory cell array,
• wherein the adjoining ones of said first, second, and third processing circuits can couple to the same data lines of said first memory cell array, and
• wherein said second parallel data transfer circuit selects one of said first group, second group, and third group data lines of said plurality of data lines of said second memory cell array.

A semiconductor integrated circuit comprising:

• first and second memory cell arrays each of which including a plurality of data line groups, a plurality of word lines intersecting said plurality of data line groups, and a plurality of memory cells disposed at desired intersections between said plurality of data line groups and said plurality of word lines;
• a first parallel data transfer circuit for transferring a plurality of first data groups in parallel from said plurality of data line groups of said first memory cell array;
• a second parallel data transfer circuit for transferring a plurality of second data groups in parallel from said plurality of data line groups of said second memory cell array, and a plurality of processing circuits for receiving said plurality of first and second data groups transferred from said first and second parallel data transfer circuits, as their input signals,
• wherein said first parallel data transfer circuit is enabled to transfer two or more of said plurality of first data groups to each of said plurality of processing circuits by sequentially selecting two or more of said plurality of first data line groups and coupling to each of said plurality of processing circuits, wherein the adjoining ones of said plurality of processing circuits can input the same data group from the same data line groups, and
• wherein said second parallel data transfer circuit is enabled to transfer two or more of said plurality of second data groups to each of said plurality of processing circuits by sequentially selecting two or more of said plurality of second data line groups and coupling to each of said plurality of processing circuits.