US 5,854,562 AGranted

Sense amplifier circuit

AssigneesHitachi, Ltd., Hitachi ULSI Engineering Corp.

InventorsHiroshi Toyoshima, Masashige Harada, Tomohiro Nagano, Yoji Nishio, Atsushi Hiraishi, Kunihiro Komiyaji, Hideharu Yahata, Kenichi Fukui, Hirofumi Zushi, Takahiro Sonoda, Haruko Kawachino, Sadayuki Morita

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Abstract

A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being of 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.

Claims10

Dependent claims

A sense amplifier circuit comprising:

first and second input signal lines;
a differential amplifying circuit including first and second NMOS transistors, with the sources thereof being connected together, for amplifying a voltage difference of first and second input signals on said first and second input signal lines;
a current source connected to the sources of said first and second NMOS transistors;
and
a latch circuit made up of a first CMOS inverter which is supplied on its input with the output of said differential amplifying circuit corresponding to said second input signal and which is directly connected to a first power line, the sources of said first and second NMOS transistors and said current source, and a second CMOS inverter which is supplied on its input with the output of said differential amplifying circuit corresponding to said first input signal and which is directly connected to said first power line, the sources of said first and second NMOS transistors and said current source, said first and second CMOS inverters having their outputs connected to the inputs of said second and first CMOS inverters, respectively.

2 more elements

Dependencies are inferred from the claim text.